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At least 379 records · Page 21

MBASIC processor

MBASIC is high-level, interactive computer language that reduces time of computer task programming. Outstanding features of MBASIC include: multiple assignments or statements in single instruction; conditional, assignment, and repetitive statement modifiers; and excellent string-handling capabilities. Two machine versions are available: UNIVAC (written in reentrant Assembler code for execution under EXEC 8) AND DEC-10 (written in Assembler code for execution under TOPS-10).

Hartley, R. B.↗

Structural dynamics of shroudless, hollow fan blades with composite in-lays

Structural and dynamic analyses are presented for a shroudless, hollow titanium fan blade proposed for future use in aircraft turbine engines. The blade was modeled and analyzed using the composite blade structural analysis computer program (COBSTRAN); an integrated program consisting of mesh generators, composite mechanics codes, NASTRAN, and pre- and post-processors. Vibration and impact analyses are presented. The vibration analysis was conducted with COBSTRAN. Results show the effect of the centrifugal force field on frequencies, twist, and blade camber. Bird impact analysis was performed with the multi-mode blade impact computer program. This program uses the geometric model and modal analysis from the COBSTRAN vibration analysis to determine the gross impact response of the fan blades to bird strikes. The structural performance of this blade is also compared to a blade of similar design but with composite in-lays on the outer surface. Results show that the composite in-lays can be selected (designed) to substantially modify the mechanical performance of the shroudless, hollow fan blade.

Aiello, R. A.↗

A general multiblock Euler code for propulsion integration. Volume 2: User guide for BCON, pre-processor for grid generation and GMBE

The BCON is a menu-driven graphics interface program whose input consists of strings or arrays of points generated from a computer aided design (CAD) tool or any other surface geometry source. The user needs to design the block topology and prepare the surface geometry definition and surface grids separately. The BCON generates input files that contain the block definitions and the block relationships required for generating a multiblock volume grid with the EAGLE grid generation package. The BCON also generates the block boundary conditions file which is used along with the block relationship file as input for the general multiblock Euler (GMBE) code (GMBE, volumes 1 and 3).

Su, T. Y.↗

Automatic data partitioning on distributed memory multicomputers

Distributed-memory parallel computers are increasingly being used to provide high levels of performance for scientific applications. Unfortunately, such machines are not very easy to program. A number of research efforts seek to alleviate this problem by developing compilers that take over the task of generating communication. The communication overheads and the extent of parallelism exploited in the resulting target program are determined largely by the manner in which data is partitioned across different processors of the machine. Most of the compilers provide no assistance to the programmer in the crucial task of determining a good data partitioning scheme. A novel approach is presented, the constraints-based approach, to the problem of automatic data partitioning for numeric programs. In this approach, the compiler identifies some desirable requirements on the distribution of various arrays being referenced in each statement, based on performance considerations. These desirable requirements are referred to as constraints. For each constraint, the compiler determines a quality measure that captures its importance with respect to the performance of the program. The quality measure is obtained through static performance estimation, without actually generating the target data-parallel program with explicit communication. Each data distribution decision is taken by combining all the relevant constraints. The compiler attempts to resolve any conflicts between constraints such that the overall execution time of the parallel program is minimized. This approach has been implemented as part of a compiler called Paradigm, that accepts Fortran 77 programs, and specifies the partitioning scheme to be used for each array in the program. We have obtained results on some programs taken from the Linpack and Eispack libraries, and the Perfect Benchmarks. These results are quite promising, and demonstrate the feasibility of automatic data partitioning for a significant class of scientific application programs with regular computations.

Gupta, Manish↗

Putting the 'super' in supercomputers

Computers used for numerical simulations of physical phenomena, e.g., flowfields, meteorology, structural analysis, etc., replace physical experiments that are too expensive or impossible to perform. The problems considered continually become increasingly more complex and thus demand faster processing times to do all necessary computations. The effects components technologies have on computer speed are leveling off, leaving new architectures and programming as the only currently viable means to upgrade speed. Parallel computations, either in the form of array processors, assembly line processing or multiprocessors are being explored using existing microprocessor technologies. Slower hardware configurations can also be made equivalent to faster supercomputers by economic programming. The availability of rudimentary parallel architecture supercomputers for general industrial use is increasing. Scientific applications continue to drive the development of more sophisticated parallel machines.

Schulbach, C.↗

Fault-Tolerant Software-Defined Radio on Manycore

Software-defined radio (SDR) platforms generally rely on field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), but such architectures require significant software development. In addition, application demands for radiation mitigation and fault tolerance exacerbate programming challenges. MaXentric Technologies, LLC, has developed a manycore-based SDR technology that provides 100 times the throughput of conventional radiationhardened general purpose processors. Manycore systems (30-100 cores and beyond) have the potential to provide high processing performance at error rates that are equivalent to current space-deployed uniprocessor systems. MaXentric's innovation is a highly flexible radio, providing over-the-air reconfiguration; adaptability; and uninterrupted, real-time, multimode operation. The technology is also compliant with NASA's Space Telecommunications Radio System (STRS) architecture. In addition to its many uses within NASA communications, the SDR can also serve as a highly programmable research-stage prototyping device for new waveforms and other communications technologies. It can also support noncommunication codes on its multicore processor, collocated with the communications workload-reducing the size, weight, and power of the overall system by aggregating processing jobs to a single board computer.

Ricketts, Scott↗

Ion Thruster and Power Processor Developed for the Deep Space 1 Mission

The NASA Solar Electric Propulsion Technology Applications Readiness (NSTAR) Program has provided a single-string primary propulsion system to NASA's Deep Space 1 spacecraft. This spacecraft will carry about 81 kg of xenon propellant for the ion thruster, which can be throttled down from 2.3 to 0.5 kW as the spacecraft moves away from the Sun. The propellant load will provide about 20 months of propulsion at the one-half power throttle setpoint of 1.2 kW. This mission will validate the 2.5-kW ion propulsion system and will fly by the asteroid 1992 KD in 1999. If funding permits, Deep Space 1 also will encounter comets Wilson-Harrington and Borrelly in 2001. NASA Lewis Research Center's On-Board Propulsion Branch was responsible for the development of the 30-cm-diameter ion thruster, the 2.5-kW power processor unit (PPU), and the Digital Control and Interface Unit (DCIU) that controls the PPU/thruster/feed system and provides data and recovery from fault conditions. Lewis transferred the thruster and PPU technologies to the Hughes Electron Dynamics Division, which was selected to build two sets of flight thrusters, as well as the PPU's and DCIU's. Hughes subcontracted the DCIU development to Spectrum Astro Incorporated. The Jet Propulsion Laboratory (JPL) was primarily responsible for the NSTAR project management, thruster lifetests, the feed system, diagnostics, and the propulsion subsystem integration. A total of four engineering model thrusters and three breadboard PPU's were built, integrated, and tested. More than 50 development tests were conducted along with thruster design verification tests of 2000 and 1000 hours. In addition, an 8000-hr life demonstration test was successfully completed and demonstrated wear-rates consistent with full-power lifetimes in excess of 12,000 hours.

Sovey, James S.↗

Numerical algorithms for finite element computations on arrays of microprocessors

The development of a multicolored successive over relaxation (SOR) program for the finite element machine is discussed. The multicolored SOR method uses a generalization of the classical Red/Black grid point ordering for the SOR method. These multicolored orderings have the advantage of allowing the SOR method to be implemented as a Jacobi method, which is ideal for arrays of processors, but still enjoy the greater rate of convergence of the SOR method. The program solves a general second order self adjoint elliptic problem on a square region with Dirichlet boundary conditions, discretized by quadratic elements on triangular regions. For this general problem and discretization, six colors are necessary for the multicolored method to operate efficiently. The specific problem that was solved using the six color program was Poisson's equation; for Poisson's equation, three colors are necessary but six may be used. In general, the number of colors needed is a function of the differential equation, the region and boundary conditions, and the particular finite element used for the discretization.

Ortega, J. M.↗

Formulation of consumables management models. Development approach for the mission planning processor working model

The mission planning processor is a user oriented tool for consumables management and is part of the total consumables subsystem management concept. The approach to be used in developing a working model of the mission planning processor is documented. The approach includes top-down design, structured programming techniques, and application of NASA approved software development standards. This development approach: (1) promotes cost effective software development, (2) enhances the quality and reliability of the working model, (3) encourages the sharing of the working model through a standard approach, and (4) promotes portability of the working model to other computer systems.

Connelly, L. C.↗

Maintaining an expert system for the Hubble Space Telescope ground support

The transformation portion of the Hubble Space Telescope (HST) Proposal Entry Processor System converts astronomer-oriented description of a scientific observing program into a detailed description of the parameters needed for planning and scheduling. The transformation system is one of a very few rulebased expert systems that has ever entered an operational phase. The day to day operations of the system and its rulebase are no longer the responsibility of the original developer. As a result, software engineering properties of the rulebased approach become more important. Maintenance issues associated with the coupling of rules within a rulebased system are discussed and a method is offered for partitioning a rulebase so that the amount of knowledge needed to modify the rulebase is minimized. This method is also used to develop a measure of the coupling strength of the rulebase.

Lindenmayer, Kelly↗

The Automatic Parallelisation of Scientific Application Codes Using a Computer Aided Parallelisation Toolkit

The shared-memory programming model is a very effective way to achieve parallelism on shared memory parallel computers. Historically, the lack of a programming standard for using directives and the rather limited performance due to scalability have affected the take-up of this programming model approach. Significant progress has been made in hardware and software technologies, as a result the performance of parallel programs with compiler directives has also made improvements. The introduction of an industrial standard for shared-memory programming with directives, OpenMP, has also addressed the issue of portability. In this study, we have extended the computer aided parallelization toolkit (developed at the University of Greenwich), to automatically generate OpenMP based parallel programs with nominal user assistance. We outline the way in which loop types are categorized and how efficient OpenMP directives can be defined and placed using the in-depth interprocedural analysis that is carried out by the toolkit. We also discuss the application of the toolkit on the NAS Parallel Benchmarks and a number of real-world application codes. This work not only demonstrates the great potential of using the toolkit to quickly parallelize serial programs but also the good performance achievable on up to 300 processors for hybrid message passing and directive-based parallelizations.

Ierotheou, C.↗

Real-Time Cognitive Computing Architecture for Data Fusion in a Dynamic Environment

A novel cognitive computing architecture is conceptualized for processing multiple channels of multi-modal sensory data streams simultaneously, and fusing the information in real time to generate intelligent reaction sequences. This unique architecture is capable of assimilating parallel data streams that could be analog, digital, synchronous/asynchronous, and could be programmed to act as a knowledge synthesizer and/or an "intelligent perception" processor. In this architecture, the bio-inspired models of visual pathway and olfactory receptor processing are combined as processing components, to achieve the composite function of "searching for a source of food while avoiding the predator." The architecture is particularly suited for scene analysis from visual data and odorant.

Duong, Tuan A.↗

Implementing Access to Data Distributed on Many Processors

A reference architecture is defined for an object-oriented implementation of domains, arrays, and distributions written in the programming language Chapel. This technology primarily addresses domains that contain arrays that have regular index sets with the low-level implementation details being beyond the scope of this discussion. What is defined is a complete set of object-oriented operators that allows one to perform data distributions for domain arrays involving regular arithmetic index sets. What is unique is that these operators allow for the arbitrary regions of the arrays to be fragmented and distributed across multiple processors with a single point of access giving the programmer the illusion that all the elements are collocated on a single processor. Today's massively parallel High Productivity Computing Systems (HPCS) are characterized by a modular structure, with a large number of processing and memory units connected by a high-speed network. Locality of access as well as load balancing are primary concerns in these systems that are typically used for high-performance scientific computation. Data distributions address these issues by providing a range of methods for spreading large data sets across the components of a system. Over the past two decades, many languages, systems, tools, and libraries have been developed for the support of distributions. Since the performance of data parallel applications is directly influenced by the distribution strategy, users often resort to low-level programming models that allow fine-tuning of the distribution aspects affecting performance, but, at the same time, are tedious and error-prone. This technology presents a reusable design of a data-distribution framework for data parallel high-performance applications. Distributions are a means to express locality in systems composed of large numbers of processor and memory components connected by a network. Since distributions have a great effect on the performance of applications, it is important that the distribution strategy is flexible, so its behavior can change depending on the needs of the application. At the same time, high productivity concerns require that the user be shielded from error-prone, tedious details such as communication and synchronization.

James, Mark↗

A Comparison of Three Programming Models for Adaptive Applications

We study the performance and programming effort for two major classes of adaptive applications under three leading parallel programming models. We find that all three models can achieve scalable performance on the state-of-the-art multiprocessor machines. The basic parallel algorithms needed for different programming models to deliver their best performance are similar, but the implementations differ greatly, far beyond the fact of using explicit messages versus implicit loads/stores. Compared with MPI and SHMEM, CC-SAS (cache-coherent shared address space) provides substantial ease of programming at the conceptual and program orchestration level, which often leads to the performance gain. However it may also suffer from the poor spatial locality of physically distributed shared data on large number of processors. Our CC-SAS implementation of the PARMETIS partitioner itself runs faster than in the other two programming models, and generates more balanced result for our application.

Shan, Hong-Zhang↗

Supporting shared data structures on distributed memory architectures

Programming nonshared memory systems is more difficult than programming shared memory systems, since there is no support for shared data structures. Current programming languages for distributed memory architectures force the user to decompose all data structures into separate pieces, with each piece owned by one of the processors in the machine, and with all communication explicitly specified by low-level message-passing primitives. A new programming environment is presented for distributed memory architectures, providing a global name space and allowing direct access to remote parts of data values. The analysis and program transformations required to implement this environment are described, and the efficiency of the resulting code on the NCUBE/7 and IPSC/2 hypercubes are described.

Koelbel, Charles↗

Trajectory optimization for real-time guidance. I - Time-varying LQR on a parallel processor

A key algorithmic element of a real-time trajectory optimization hardware/software implementation, the quadratic program (QP) solver element, is presented. The purpose of the effort is to make nonlinear trajectory optimization fast enough to provide real-time commands during guidance of a vehicle such as an aeromaneuvering orbiter. Many methods of nonlinear programming require the solution of a QP at each iteration. In the trajectory optimization case the QP has a special dynamic programming structure, a LQR-like structure. QP algorithm speed is increased by taking advantage of this special structure and by parallel implementation.

Psiaki, Mark L.↗

Satellite baseband processor test performance summary

A satellite baseband processor (BBP) has been developed for the NASA Lewis 30/20 GHz Satellite Communications Program. The BBP design, reported elsewhere, has been implemented in a proof-of-concept (POC) model. The results of the laboratory system tests of the POC are summarized. Bit error rate test results are presented for the FDM/TDMA communication system operating at 27.5, 110, and 550 Mbps over a variety of operating conditions. The results clearly demonstrate the applicability of baseband processing to future high capacity satellite communication system concepts. A brief description of the system concept, its function, and the role of the baseband processor are presented. The test conditions and means of simulation are also described. The methods of test evaluation and their significance in a system context are given.

Shaneyfelt, J. T.↗

Initial experience with distributing structural calculations among computers operating in parallel

An existing program is currently being adapted to perform finite element analysis by distributing substructures over a network of four Apple IIe microcomputers connected to a shared disk. In this network, one microcomputer controls the entire process while the others perform the analysis on each substructure in parallel. This substructure analysis is used in an iterative, fully stressed, structural resizing procedure. This procedure allows experimentatation with resizing in which all analyses are not completed during a single iteration. This research gives some insight on how to configure multidiscriplinary analysis and optimization procedures for decomposable engineering systems using either high performance engineering workstations or a parallel processor supercomputer. In addition, the operational experience gained facilitates the implementation of analysis programs on these new computers when they become available in an engineering environment.

Rogers, J. L., Jr.↗