Satellite baseband processor test performance summary

Abstract

A satellite baseband processor (BBP) has been developed for the NASA Lewis 30/20 GHz Satellite Communications Program. The BBP design, reported elsewhere, has been implemented in a proof-of-concept (POC) model. The results of the laboratory system tests of the POC are summarized. Bit error rate test results are presented for the FDM/TDMA communication system operating at 27.5, 110, and 550 Mbps over a variety of operating conditions. The results clearly demonstrate the applicability of baseband processing to future high capacity satellite communication system concepts. A brief description of the system concept, its function, and the role of the baseband processor are presented. The test conditions and means of simulation are also described. The methods of test evaluation and their significance in a system context are given.