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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 379 records · Page 21
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Cyclops - The JPL AIRSAR synoptic processor

Capability for synoptic, or wide-area, SAR processing has been added to the JPL Aircraft Synthetic Aperture Radar System (AIRSAR) by means of the CYCLOPS synoptic processor. Polarimetric requirements have been relaxed so that a single node in the system can process SAR data with a throughput of three channels in 3.75 hours. Each channel consists of five minutes of full-range-swath data chosen from the twelve available AIRSAR polarization channels. Processed data consists of 16-look, 16-meter resolution imagery with a swath size of 60 km. The processor fully utilizes the available Doppler bandwidth and provides processing options for range migration correction, zero-Doppler deskew, frequency registration, and radiometric correction. The detected-power output product is scaled so as to provide sigma zero radiometric calibration.

Taylor, Victor B.↗
NASA NTRS1993

Dynamically reconfigurable optical morphological processor and its applications

An innovative optically implemented morphological processor is introduced. With the use of a large space-bandwidth-product Dammann grating and a high-speed shutter spatial light modulator, effective structuring element with large size and arbitrary shape can be constructed with dynamic reconfigurability. This reconfigurability is a major improvement over the conventional correlator-based morphological processor in which fixed holographic filters are used as structuring elements (Casasent and Botha, 1988). A novel two-dimensional thresholding photodetector array, capable of performing parallel thresholding and feedback, is utilized in this system and makes possible the implementation of many complex morphological operations requiring iterative feedbacks and full programmability. The optical architecture and the principle of operation are presented. Experimental demonstration of binary image morphological erosion, dilation, opening, and closing are also demonstrated. A technique for extending this technique to gray-scale image using thresholding decomposition technique is also discussed.

Chao, Tien-Hsin↗
NASA NTRS1991

SPROC: A multiple-processor DSP IC

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Davis, R.↗
NASA NTRS1991

A modified reconfigurable data path processor

High throughput is an overriding factor dictating system performance. A configurable data processor is presented which can be modified to optimize performance for a wide class of problems. The new processor is specifically designed for arbitrary data path operations and can be dynamically reconfigured.

Ganesh, G.↗
NASA NTRS1993

Multiple-fold clustered processor mesh array

The multiple-fold clustered processor mesh array is a triangular organization of clustered processing elements. This multiple-fold array maintains functional equivalence to the nearest neighbor mesh computer with uni-directional interprocessor communications, but with half the number of connection wires. In addition, the connectivity of the multiple-folded organization is superior to the standard square mesh due to the improved connectivity between the clustered processors. One of the primary application areas targeted is High Performance Architectures for image processing.

Pechanek, Gerald G.↗
NASA NTRS1993

Towards the formal verification of the requirements and design of a processor interface unit: HOL listings

This technical report contains the Higher-Order Logic (HOL) listings of the partial verification of the requirements and design for a commercially developed processor interface unit (PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault tolerant computer system. This system, the Fault Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU verification as it currently exists. Section two of this report contains general-purpose HOL theories and definitions that support the PIU verification. These include arithmetic theories dealing with inequalities and associativity, and a collection of tactics used in the PIU proofs. Section three contains the HOL listings for the completed PIU design verification. Section 4 contains the HOL listings for the partial requirements verification of the P-Port.

Fura, David A.↗
NASA NTRS1994

Interpreter composition issues in the formal verification of a processor-memory module

This report describes interpreter composition techniques suitable for the formal specification and verification of a processor-memory module using the HOL theorem proving system. The processor-memory module is a multichip subsystem within a fault-tolerant embedded system under development within the Boeing Defense and Space Group. Modeling and verification methods were developed that permit provably secure composition at the transaction-level of specification, significantly reducing the complexity of the hierarchical verification of the system.

Fura, David A.↗
NASA NTRS1993

Embedded Data Processor and Portable Computer Technology testbeds

Attention is given to current activities in the Embedded Data Processor and Portable Computer Technology testbed configurations that are part of the Advanced Data Systems Architectures Testbed at the Information Sciences Division at NASA Ames Research Center. The Embedded Data Processor Testbed evaluates advanced microprocessors for potential use in mission and payload applications within the Space Station Freedom Program. The Portable Computer Technology (PCT) Testbed integrates and demonstrates advanced portable computing devices and data system architectures. The PCT Testbed uses both commercial and custom-developed devices to demonstrate the feasibility of functional expansion and networking for portable computers in flight missions.

Alena, Richard↗
NASA NTRS1994

Development Status of the NASA 30-cm Ion Thruster and Power Processor

Xenon ion propulsion systems are being developed by NASA Lewis Research Center and the Jet Propulsion Laboratory to provide flight qualification and validation for planetary and earth-orbital missions. In the ground-test element of this program, light-weight (less than 7 kg), 30 cm diameter ion thrusters have been fabricated, and preliminary design verification tests have been conducted. At 2.3 kW, the thrust, specific impulse, and efficiency were 91 mN, 3300 s, and 0.65, respectively. An engineering model thruster is now undergoing a 2000 h wear-test. A breadboard power processor is being developed to operate from an 80 V to 120 V power bus with inverter switching frequencies of 50 kHz. The power processor design is a pathfinder and uses only three power supplies. The projected specific mass of a flight unit is about 5 kg/kW with an efficiency of 0.92 at the full-power of 2.5 kW. Preliminary integration tests of the neutralizer power supply and the ion thruster have been completed. Fabrication and test of the discharge and beam/accelerator power stages are underway.

Sovey, James S.↗
NASA NTRS1995

Scheduling time-critical graphics on multiple processors

This paper describes an algorithm for the scheduling of time-critical rendering and computation tasks on single- and multiple-processor architectures, with minimal pipelining. It was developed to manage scientific visualization scenes consisting of hundreds of objects, each of which can be computed and displayed at thousands of possible resolution levels. The algorithm generates the time-critical schedule using progressive-refinement techniques; it always returns a feasible schedule and, when allowed to run to completion, produces a near-optimal schedule which takes advantage of almost the entire multiple-processor system.

Meyer, Tom W.↗
NASA NTRS1995

Prototype Focal-Plane-Array Optoelectronic Image Processor

Prototype very-large-scale integrated (VLSI) planar array of optoelectronic processing elements combines speed of optical input and output with flexibility of reconfiguration (programmability) of electronic processing medium. Basic concept of processor described in "Optical-Input, Optical-Output Morphological Processor" (NPO-18174). Performs binary operations on binary (black and white) images. Each processing element corresponds to one picture element of image and located at that picture element. Includes input-plane photodetector in form of parasitic phototransistor part of processing circuit. Output of each processing circuit used to modulate one picture element in output-plane liquid-crystal display device. Intended to implement morphological processing algorithms that transform image into set of features suitable for high-level processing; e.g., recognition.

Fang, Wai-Chi↗
NASA NTRS1995

CCD/CID Processors Would Offer Greater Precision

Charge-coupled-device/charge-injection-device (CCD/CID) data processors of proposed type offer advantages of massively parallel computational architecture and high computational speed typical of older CCD/CID data processors, but with increased precision. Useful in performing matrix vector multiplications in variety of applications, including solving partial differential equations, processing signal and image data, control computations, and neural-network simulations. Greater precision of proposed devices help to ensure accuracy in CCD/CID implementations of pseudospectral neural networks - particular class of artificial neural networks especially suited to solving nonlinear differential equations.

Barhen, Jacob↗
NASA NTRS1996

Design and Development of a Baseband Processor for the Advanced Communications Technology Satellite

This paper describes the implementation of the operational baseband processor (BBP) subsystem on board the NASA Advanced Communications Technology Satellite (ACTS). The BBP supports the network consisting of the NASA ground station (NGS) low burst rate (LBR) terminals, and the T1 very small aperture terminals (VSAT's), to provide flexible, demand assigned satellite switched (SS), baseband processed frequency division modulated (FDM)/time division multiple access (TDMA) operations. This paper presents an overview of the baseband processor and includes a description of the data flow, functional block diagrams, and a discussion of the implementation of BBP. A discussion of the supporting technologies for the BBP is presented. A brief summary of BBP-level performance testing is also presented. Finally, a discussion of the implications of current technology on the BBP design, if it were to be developed today, is presented.

Lee, Kerry D.↗
NASA NTRS1991

An Object-oriented Query Processor that Produces Monotonically Improving Approximate Answers

The paper describes an object-oriented query processor that makes approximate answers available if there is not enough time to produce an exact answer or if part of the database is unavailable. The accuracy of the approximate result produces improves monotonically with the amount of data retrieved to produce the result. The query processing algorithm is based on an approximate relational data model and works within a standard relational algebra framework. The query processor maintains an object-oriented view on an underlying level and can be implemented on a relational database system with little change to the relational architecture. We show how a monotone query processing strategy can be implemented, making effective use of semantic information presented by the object-oriented view.

Vrbsky, S. V.↗
NASA NTRS1996

An Automated Mapping Processor using C-Band Interferometric SAR Data

We describe a processor which has been implemented to generate map products starting from C-band interferometric data. The first stage of the processor consists of the conventional interferometric synthetic aperture radar (SAR) processing producing a digital elevation model (DEM) and a SAR brightness image in sensor coordinates. In the second stage of processing, a land use classification map is obtained by using the DEM, brightness, and interferometric correlation layers. Auxiliary layers which include a drainage layer, a height gradient layer, a height error layer, an estimated penetration layer, and a shaded relief layer are also computed. In the final step, all UTM collocated layers are combined in a geographical information system (GIS) which allows for both hard copy map products and digital applications.

Rodriguez, E.↗
NASA NTRS1996

Digital Parallel Processor Array for Optimum Path Planning

The invention computes the optimum path across a terrain or topology represented by an array of parallel processor cells interconnected between neighboring cells by links extending along different directions to the neighboring cells. Such an array is preferably implemented as a high-speed integrated circuit. The computation of the optimum path is accomplished by, in each cell, receiving stimulus signals from neighboring cells along corresponding directions, determining and storing the identity of a direction along which the first stimulus signal is received, broadcasting a subsequent stimulus signal to the neighboring cells after a predetermined delay time, whereby stimulus signals propagate throughout the array from a starting one of the cells. After propagation of the stimulus signal throughout the array, a master processor traces back from a selected destination cell to the starting cell along an optimum path of the cells in accordance with the identity of the directions stored in each of the cells.

Kremeny, Sabrina E.↗
NASA NTRS1996

An Automated Mapping Processor Using C-Band Interferometric SAR Data

We present the description of a processor which has been implemented to generate map products starting from C-band interferometric data. The first stage of the processor consists of the conventional interferometric SAR processing producing a Digital Elevation Model (DEMs) and a SAR brightness image in sensor coordinates. In the second stage of processing, a land use classification map is obtained by using the DEM, brightness, and interferometric correlation layers. Auxiliary layers which include a drainage layer, a height gradient layer, a height error layer, an estimated penetration layer, and a shaded relief layer are also computed. In the final step, all UTM collocated layers are combined in a GIS system which allows for both hard copy map products and for digital applications.

Rodriguez, E.↗