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At least 379 records · Page 21

All sources NASA NTRS DOE OSTI

DOE OSTI2023

Prototype Design of Global Common Module for ATLAS Experiment’s Phase-II Upgrade

A new Global Trigger subsystem will be installed in the Level-0 Trigger as part of HL-LHC Upgrade of ATLAS during the upcoming Long-Shutdown 3. It will feature new and improved trigger hardware and algorithms, and an increased maximum output rate of 1 MHz. The Global Trigger will run offline-like trigger algorithms on full-granularity data, gathered from several sub-detectors and trigger-processing subsystems. A single Global Common Module (GCM) hardware is implemented across the Global Trigger system to be used as Multiplexer Processor, Global Event Processor and CTP Interface (gCTPi). This common hardware platform method will minimize the complexity of the firmware and simplify the system design and long-term maintenance. The GCM prototype is an ATCA front form factor board with two Xilinx Virtex UltraScale+ FPGA VU13P and one ZYNQ UltraScale+ FPGA ZU19EG and seventeen 25.78125 Gb/s FireFly duplex optical modules on it. The total power consumption of this board must be less than 350 W, and the temperature of the optical modules should be less than 70 °C in the worst case. The VU13Ps serve as algorithms processor nodes such as MUX, GEP and gCTPi, and the ZU19EG with Peta Linux OS running on it, is used as Command/Control/Readout Unit to configure and monitor the board and communicate with the ATLAS Detector Control System (DCS). The development of an ATCA blade with three large FPGAs and about 200 optical links running at 25Gb/s is a very challenging task, and the successful test results have demonstrated this GCM prototype as an advancement of state-of-the-art electronics module design in HEP experiments. This paper presents the hardware design considerations, functionalities, and performance test results of this GCM prototype.

47 OTHER INSTRUMENTATION↗

DOE OSTI2025

End-to-End Workflow for Machine-Learning-Based Qubit Readout With QICK and hls4ml

In this article, we present an end-to-end workflow for superconducting qubit readout that embeds codesigned neural networks into the quantum instrumentation control kit (QICK). Capitalizing on the custom firmware and software of the QICK platform, which is built on Xilinx radiofrequency system-on-chip field-programmable gate arrays (FPGAs), we aim to leverage machine learning (ML) to address critical challenges in qubit readout accuracy and scalability. The workflow utilizes the hls4ml package and employs quantization-aware training to translate ML models into hardware-efficient FPGA implementations via user-friendly Python application programming interfaces. We experimentally demonstrate the design, optimization, and integration of an ML algorithm for single transmon qubit readout, achieving 96% single-shot fidelity with a latency of 32.25 ns and less than 16% FPGA lookup table resource utilization. Our results offer the community an accessible workflow to advance ML-driven readout and adaptive control in quantum information processing applications.

42 ENGINEERING↗

DOE OSTI2022

Design and analysis of CXL performance models for tightly-coupled heterogeneous computing

Truly heterogeneous systems enable partitioned workloads to be mapped to the hardware that nets the best performance. However, current practice requires that inter-device communication between different vendors' hardware use host memory as an intermediary step. To date, there are no widely adopted solutions that allow accelerators to directly transfer data. A new cache-coherent protocol, CXL, aims to facilitate easier, fine-grained sharing between accelerators. In this work we analyze existing methods for designing heterogeneous applications that target GPUs and FPGAs working collaboratively, followed by an exploration to show the benefits of a CXL-enabled system. Specifically, we develop a test application that utilizes both an NVIDIA P100 GPU and a Xilinx U250 FPGA to show current communication limitations. From this application, we capture overall execution time and throughput measurements on the FPGA and GPU. We use these measurements as inputs to novel CXL performance models to show that using CXL caching instead of host memory results in a 1.31X speedup, while a more tightly-coupled pipelined implementation using CXL-enabled hardware would result in a speedup of 1.45X.

Cabrera, Anthony↗

DOE OSTI2023

High-Level Synthesis of Irregular Applications: A Case Study on Influence Maximization

The Influence Maximization problem is the problem of identifying a small cohort of actors from a broader population that, when initially activated in a diffusion process, are expected to result in a large number of activations in the population. While the problem is known to be NP-hard, several approximation algorithms have been devised by leveraging its submodular structure. While these algorithms are theoretically efficient, they are computationally very expensive in practice. This work advances the current state-of-the-art parallelization scheme for the IMM algorithm by devising the adoption of custom hardware accelerators implemented on FPGAs by leveraging High Level Synthesis from OpenCL. We study the performance of our proposed approach by exploring optimizations tailored at improving the parallel efficiency of the accelerators and highlight their effects and limitations in accelerating complex graph analytic applications. Our experimental evaluation shows that FPGA acceleration can improve the performance of the LT diffusion model up to 1.72x for the entire application and up to 2.90x for its most important kernel with respect to a CPU only parallel execution. The FPGA acceleration of the LT model shows also a 1.54x reduction in energy consumption when compared to a parallel CPU only run.

Neff, Reece W.↗

DOE OSTI2021

Qubit Control System (QubiC) v1.0

We design a modular FPGA (field-programmable gate array) based system called QubiC to control and measure a superconducting quantum processing unit. The system includes room temperature electronics hardware, FPGA gateware, and engineering software.

Huang, Gang↗

DOE OSTI2021

XVC FTDI JTAG v1.0

the Xilinx tools relay on a component on the board (FTDI chip) to have a small memory from a particular manufacturer (Digilent) to serve as a bridge to the FPGA. What the software we're requesting to release simply does is to run between the Xilinx tools (one of them is called Vivado but there are others) and our boards so that we don't need that memory on our boards. The protocol the software uses to communicate with the Xilinx tools is called XVC (Xilinx Virtual Cable). This server code runs on the computer that is physically connected to the FPGA board, but the Xilinx tools that communicate with it can run either on that computer or some other computer connected to it over the network, this is where the network component comes into play.

Norum, William↗

DOE OSTI2024

Control System for RF OPM

SAND2025-01910O This software built in LabVIEW FPGA provides experimental control of the RF OPM prototype via a reconfigurable NI I/O card. It samples the analog input, processes it on the FPGA in real time, and generates control and feedback outputs to control and optimize the operation of the device. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

Bainbridge, Jonathan↗

DOE OSTI2026

Surrogate model for third-integer resonance extraction at the Fermilab Delivery Ring

We present an ongoing work in which a surrogate model is being developed to reproduce the response dynamics of the third-integer resonant extraction process in the Delivery Ring (DR) at Fermilab. This is in pursuit of smoothly extracting circulating beam to the Mu2e Experiment’s production target, whereby the goal is to extract a uniform slice of the circulating 1e12 protons in the DR over 25,000 turns (43 ms). The DR contains 3 harmonic sextupoles that excite a third-integer resonance and three fast, tune-ramping quadrupole magnets that drive the horizontal tune towards the 29/3 resonance. In our initial work, the surrogate model trains on a semi-analytical simulation provided in the same format as live data. Using Reinforcement Learning (and other potential ML methods), the trained surrogate acts as the “environment” in which a simple ML control agent could learn to dynamically adjust the quadrupole ramp at 430 break points within the 43 microsecond spill window. The controller will be hosted on a dedicated Arria 10 FPGA. In this work, we report the accuracy and fidelity of the surrogate model in comparison to the response dynamics of the physics simulator.

Narayanan, Aakaash [Fermilab]↗

DOE OSTI2024

Electron Density Measurements Using USPR (Final Scientific/Technical Report)

UC Davis has fabricated an ultrashort pulse reflectometer (USPR) diagnostic instrument for electron density profile measurements on compact, short duration, magnetically-confined fusion-energy concept devices such as spheromaks and FRCs. The USPR system transmits extremely short duration (~few nsec) chirped waveforms that together span 29 to 75 GHz. These chirped waveforms illuminate and reflect from the target plasma, with each frequency component reflecting from a different density layer (higher frequencies probe deeper into the plasma before reflecting). The reflected waveforms are split into roughly 42 different frequencies; time-of-flight (TOF) measurements made at each frequency with high resolution (~25 psec measurement resolution which corresponds to ~5 mm). These TOF data may then be inverted via software to generate electron density profiles with high time resolution (~10 μsec). At the heart of the system is a field programmable gate array (FPGA) based controller which collects and processes all of the USPR data in addition to generating all of the control signals required for maximum flexibility. The FPGA controller has the software flexibility to be easily reconfigured for different plasma devices, and the entire system sufficiently compact to be easily and quickly transported between devices. A high speed impulse generator was transformed into a set of three ultrashort pulse transmitter chirps using a combination of dispersive waveguide, frequency doublers and high-pass filters. A mm-wave controller was fabricated to sequentially switch between the three chirps, directing the chirps one-by-one to three different mm-wave assemblies spanning 29-75 GHz. Each mm-wave assembly consists of a high power active multiplier chain which converts the transmitter chirp to higher frequencies, and a broadband mixer which downconverts the reflected waveform to the 2-18 GHz range of the UPSR receiver. The 16-channel receiver (shared by all 3 mm-wave assemblies) was fabricated employing custom TOF modules capable of operating at a high 1 MHz sampling rate. Laboratory testing of the full system revealed the presence of unwanted harmonics from the multiplication process, with interference observed in the downconverted reflections at selected frequency channels that could not be completely filtered out. Additional interference effects arising from internal reflections within the mm-wave assemblies were minimized using a high-speed switch which served to “gate out” much of these reflections. The USPR diagnostic was transported and installed onto the HIT-SIU plasma device, becoming operational on 11/08/2022. Although designed to span 3 distinct mm-wave bands, the HIT-SIU plasmas at this time were sufficiently low density such that only the lowest of the three bands was likely to have strong plasma reflections. The system was then set to operate on only the lowest band (assembly #1), with data collected every 1 μsec rather than 3 μsec which would have been the case when cycling through all three bands. Connected to HIT-SIU, time-varying plasma reflections were observed on 9 of 16 possible frequency channels. Close examination of the data collected revealed issues previously unobserved in laboratory testing, associated with (a) reflections from the small aperture horns required for operation within the HIT-SIU device, and (b) a dependence of the recorded TOF with the threshold voltage of a given channel. Plans were made to address each of these issues before undertaking any future campaigns.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

DOE OSTI2024

wa-hls4ml: A GNN Surrogate Model for hls4ml

Recent advancements in use of machine learning techniques on field-programmable gate arrays (FPGAs) have allowed for implementation of embedded neural networks with extremely low latency. This is invaluable for particle detectors at the Large Hadron Collider, where latency and used area must be strictly bounded. The hls4ml framework is a procedure for converting from trained machine learning model software, to a synthesis result that can be used on an FPGA. However, running the pipeline is a time-consuming procedure, and there is a strong risk of failure. In particular, it is possible that the model is unable to be converted into a synthesis result, or that the resource consumption of the model will exceed the resources of the target FPGA. To aid with this development, we introduce wa-hls4ml, a surrogate model which uses a graph neural network to emulate the structure of the source models. The goal is to estimate the chance of success and resource consumption of an arbitrary model when passed through the hls4ml procedure, without the time consumption of actually running the pipeline.

43 PARTICLE ACCELERATORS↗

DOE OSTI2022

EJFAT: Towards Intelligent Compute Destination Load Balancing

To handle increased data flow, Jefferson Lab (JLab) is partnering with ESnet for development of an AI/ML directed compute work Load Balancer (LB) of UDP streamed data. The LB is FPGA based featuring dynamically configurable, low latency and high throughput destination address switching. The LB provides integration of edge and core computing to support JLab experimental programs, the Electron-Ion Collider, as well as data centers of the future. In the ESnet/JLab FPGA Accelerated Transport (EJFAT) initiative, the function of the LB Data Plane (DP) is to redirect data streams to selectable (but unknown to sender) destination hosts based on current worload and within that host to destination ports as a function of sub- stream id. This effects hierarchical scaling, first across compute machines for processing over a series of events and second, across ports so different data source sub-streams may be assigned to different processors for further parallelization. The LB Control Plane (CP) programs the DP using compute farm telemetry to direct and balance workloads across a compute cluster as the operating conditions require. While Proportional/Integrative/Derivative (PID) controllers are often seen in similar applications, here we investigate the feasibility of a Reinforcement Learning (RL) based schedule manager running in the CP to provide dynamic updates to the DP scheduling policy.

Lawrence, David↗

DOE OSTI2024

Field Programmable Gate Array-Based Reactor Protection Systems and Potential for Inclusion of Secure Elements to Improve Cybersecurity

For acceptable implementations of technologies like wireless communications, remote monitoring, etc., strong mitigations must be developed and evaluated to ensure that new attack pathways do not increase risk for Advanced Reactors. Secure Elements can be adopted and adapted for this purpose based on tamper resistance and cryptographic abilities, but research must be done to properly integrate into critical components such as FPGA-based Important to Safety systems in conjunction with current and future regulations on cyber security features in Advanced Reactors. Typically, the integration of a Secure Element happens during the POST and UEFI boot of a computing platform, performed by the Operating System, which is not possible with FPGAs because they do not include these firmware components. Work must be done to identify a reliable and secure method for integration in FPGA-based systems which lack Operating Systems and therefore complex boot procedures, system calls, etc.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2024

Field Programmable Gate Array-Based Reactor Protection Systems and Potential for Inclusion of Secure Elements to Improve Cybersecurity

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2025

Quantum Instrumentation and Control Kit (QICK) for Quantum Networks

We report the first demonstration of using the Quantum Instrumentation and Control Kit (QICK) system on RFSoC FPGA technology to drive an entangled photon pair source and to detect the photon signals. With the QICK system, we achieve high levels of performance metrics including coincidence-to-accidental ratio exceeding 150, and entanglement visibility exceeding 95%, consistent with performance metrics achieved using conventional waveform generators. We also demonstrate simultaneous detector readout using the digitization functional of QICK, achieving internal system synchronization time resolution of 3.2 ps. The work reported in this paper represents an explicit demonstration of the feasibility for replacing commercial waveform generators and time taggers with RFSoC-FPGA technology in the operation of a quantum network, representing a cost reduction of more than an order of magnitude.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2025

Radiation Effects on Network on Chips (NoC) Laboratory Directed Research and Development (LDRD) project

This project was motivated by State-of-the-Art (SOTA) technology that incorporates Network on Chips (NOC) for efficient data communication across the various computer kernels. For example, on the AMD Versal Field Programmable Gate Arrays (FPGA), an NoC has been incorporated for fast data communication from the programmable logic and other computer kernels (processing system, adaptable intelligence engines, etc.). The radiation effects on the legacy technology of this FPGA, such as the programmable logic, are well understood, and established methods exist to measure cross-sections when new families/generations are released; however, newly incorporated technologies, such as the NoC, are not fully understood and could introduce new failure points into the mission space.

36 MATERIALS SCIENCE↗

DOE OSTI2025

Development of an FGPA-Based Cavity Simulator for Testing RF Controls

LLRF is used to precisely control the amplitude and phase of the RF field in cavities. Often times, access to test the control algorithms with RF equipment, especially in the presence of beam, is limited or beyond reach. In such cases, testing must be done through computer modeling or simulations. Computer modeling is often too slow and difficult to interface with the LLRF hardware. Analog or digital cavity simulators are preferred as they allow for interaction with the LLRF controls platform in real-time, and compared to their analog counterparts, FPGA-based digital cavity simulators allow for a more adjustable and sophisticated implementation. The newly developed FPGA-based cavity simulator includes the cavity electrical model, the cavity mechanical model including Lorentz Force Detuning and microphonics, an amplifier model which can simulate real amplifier nonlinearities, and a beam model. The simulator has been validated using measurements from BNL’s CeC 704 MHz 5-cell SRF cryomodule.

43 PARTICLE ACCELERATORS↗

DOE OSTI2025

Warm Front End Upgrade for the PIP-II Linac

The warm front end for the PIP-II Linac consists of an Ion-source, an RFQ, and four buncher cavities. The LLRF systems for these were the first ones developed more than a decade ago for use at the test stands. Some were VXI crate based, and others used early generation FPGA boards that are light in resources. These LLRF systems and the one for the first superconducting cryomodule, the HWR will be upgraded with the ARRIA 10 SOC-FPGA chassis with EPICS interfaces like the rest of the PIP-II Linac. The RFQ and the HWR have unique resonance control systems which are integrated into the LLRF controller hardware. The results of the initial testing with a cavity emulator will be presented.

Reyes, Lennon [Fermilab] (ORCID:0009000891155652)↗

DOE OSTI2025

Vitis CI/CD & Containerization

Modern development flows that use tooling for automated building, testing, and deployment of software are becoming the norm for large scale software and hardware projects. These flows offer quite a few advantages that make them desirable, but when attempting to implement them for projects that use FPGAs, some complications can arise when attempting to integrate them with traditional FPGA toolchains and deployment workflows. In this poster, we present early our early efforts integrating the Vitis FPGA toolchain into a modern, Kuberentes and Github actions based CI/CD pipeline.

Hawks, Benjamin G. [Fermilab]↗