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All sources NASA NTRS DOE OSTI

DOE OSTI2025

Optimization of edge bead removal (EBR) process to enhance defect reduction in optical lithography

Defect reduction remains a critical objective in the integrated circuit manufacturing process, particularly within the highly re-entrant lithography modules where minimizing defects is crucial. Defects at the wafer edge can contaminate lithography modules and downstream processing equipment, leading to redistribution onto the wafer surface and adversely affecting overall device yield. A persistent challenge in the resist coating process is the formation of resist edge beads, driven by the strong Van der Waals attraction of excess photoresist (PR) to itself and the underlying substrate. The edge bead removal (EBR) process is a standard cleaning step designed to eliminate these edge beads and prevent potential contamination. Here, in this study, we identify the sources of EBR induced defects and additional EBR process encroachment toward edge patterning during the EBR cleaning process. This study provides a comprehensive study aimed at optimizing the EBR cleaning process to effectively eliminate EBR-induced defects, thereby enhancing overall device yield. Specifically, we identify three primary defects induced by the EBR cleaning process: rainbow-type, finger-shaped, and teardrop-type defects. Our experimental study reveals that in addition to EBR rinse time, PR cast time is crucial parameters contributing to the formation of these defects. By properly optimizing the PR cast time and EBR rinse time, we were able to remove nearly 100 % of dense clusters of defects that were easily visible even at low magnification optical microscopy throughout the wafer edge. We observed that shorter PR casting times shows edge defects caused by inefficient EBR process because of insufficient time for PR to fully settle causing superfluous PR to continue flowing toward wafer edge during EBR clearing step, leading to partial removal of PR at the wafer edge and the formation of rainbow defects. Proper optimization of both PR casting time and EBR chemistries dispense time is essential to resolve these defects, ensuring efficient EBR cleaning process and improved overall device yield.

42 ENGINEERING↗

DOE OSTI2021

GaAs Solar Cells Grown on Intentionally-Contaminated GaAs Substrates

III-V solar cells have the best performance of any semiconductor materials, but deposition of these materials relies on high-quality single crystal GaAs wafers for their superior performance. Unfortunately, the cost of these wafers makes these high-efficiency devices only accessible in high-value or niche markets. Here, we explored the effect of growing bulk GaAs crystals with lower purity input materials in order to reduce their cost. We observe that intentional impurities added to the melt before the crystal growth occurs segregate to the top of the boule. Single junction GaAs solar cells grown on wafers made from contaminated boules showed no performance degradation compared to a high-purity control wafer. These results suggest that lower purity Ga and As source materials can be used during crystal growth to reduce the cost of wafers.

41 EE - Solar Energy Technologies Office (EE-4S)↗

NASA NTRS1982

Process Research on Polycrystalline Silicon Material (PROPSM)

The investigation of the performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was continued by fabricating a set of minicell wafers on a selection of 10 cm x 10 cm wafers. A minicell wafer consists of an array of small (approximately 0.2 sq cm in area) photodiodes which are isolated from one another by a mesa structure. The junction capacitance of each minicell was used to obtain the dopant concentration, and therefore the resistivity, as a function of position across each wafer. The results indicate that there is no significant variation in resistivity with position for any of the polycrystalline wafers, whether Semix or Wacker. However, the resistivity of Semix brick 71-01E did decrease slightly from bottom to top.

Culik, J. S.↗

NASA NTRS1983

Process Research on Polycrystalline Silicon Material (PROPSM)

The performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was investigated by measuring the illuminated current voltage (I-V) characteristics of the minicell wafer set. The average short circuit current on different wafers is 3 to 14 percent lower than that of single crystal Czochralski silicon. The scatter was typically less than 3 percent. The average open circuit voltage is 20 to 60 mV less than that of single crystal silicon. The scatter in the open circuit voltage of most of the polycrystalline silicon wafers was 15 to 20 mV, although two wafers had significantly greater scatter than this value. The fill factor of both polycrystalline and single crystal silicon cells was typically in the range of 60 to 70 percent; however several polycrystalline silicon wafers have fill factor averages which are somewhat lower and have a significantly larger degree of scatter.

Culik, J. S.↗

NASA NTRS1984

Development and fabrication of a solar cell junction processing system

A processing system capable of producing solar cell junctions by ion implantation followed by pulsed electron beam annealing was developed and constructed. The machine was to be capable of processing 4-inch diameter single-crystal wafers at a rate of 10(7) wafers per year. A microcomputer-controlled pulsed electron beam annealer with a vacuum interlocked wafer transport system was designed, built and demonstrated to produce solar cell junctions on 4-inch wafers with an AMI efficiency of 12%. Experiments showed that a non-mass-analyzed (NMA) ion beam could implant 10 keV phosphorous dopant to form solar cell junctions which were equivalent to mass-analyzed implants. A NMA ion implanter, compatible with the pulsed electron beam annealer and wafer transport system was designed in detail but was not built because of program termination.

Source record↗

NASA NTRS1995

Thin Layer Composite Unimorph Ferroelectric Driver and Sensor

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled, causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

Helbaum, Richard F.↗

NASA NTRS1997

Thin Layer Composite Unimorph Ferroelectric Driver and Sensor

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

Hellbaum, Richard F.↗

NASA NTRS1997

High Frequency Interconnects on Silicon Substrates

The measured propagation constant of coplanar waveguide (CPW) on silicon wafers as a function of the line dimensions and the resistivity of the Si wafer; CPW on GaAs wafers as a function of the line dimensions, and thin film microstrip (TFMS) polyimide fabricated with polyimide on the surface of a silicon wafer is presented. It is shown that the attenuation of CPW on 2500 Omega-cm Si wafers and-of TFMS with a polyimide thickness of 4 micrometer or greater is comparable to the attenuation of similar lines on GaAs.

Ponchak, George E.↗

NASA NTRS2004

Thin layer composite unimorph ferroelectric driver and sensor

Hellbaum, Richard F.↗

NASA NTRS2008

Embossed Teflon AF Laminate Membrane Microfluidic Diaphragm Valves

A microfluidic system has been designed to survive spaceflight and to function autonomously on the Martian surface. It manipulates microscopic quantities of liquid water and performs chemical analyses on these samples to assay for the presence of molecules associated with past or present living processes. This technology lies at the core of the Urey Instrument, which is scheduled for inclusion on the Pasteur Payload of the ESA ExoMars rover mission in 2013. Fabrication processes have been developed to make the microfabricated Teflon-AF microfluidic diaphragm pumps capable of surviving extreme temperature excursions before and after exposure to liquid water. Two glass wafers are etched with features and a continuous Teflon membrane is sandwiched between them (see figure). Single valves are constructed using this geometry. The microfabricated devices are then post processed by heating the assembled device while applying pneumatic pressure to force the Teflon diaphragm against the valve seat while it is softened. After cooling the device, the embossed membrane retains this new shape. This solves previous problems with bubble introduction into the fluid flow where deformations of the membrane at the valve seat occurred during device bonding at elevated temperatures (100-150 C). The use of laminated membranes containing commercial Teflon AF 2400 sheet sandwiched between spun Teflon AF 1600 layers performed best, and were less gas permeable than Teflon AF 1600 membranes on their own. Spinning Teflon AF 1600 solution (6 percent in FLOURINERT(Registered TradeMark) FC40 solvent, 3M Company) at 500 rpm for 1.5 seconds, followed by 1,000 rpm for 3 seconds onto Borofloat glass wafers, results in a 10-micron-thick film of extremely smooth Teflon AF. This spinning process is repeated several times on flat, blank, glass wafers in order to gradually build a thick, smooth membrane. After running this process at least five times, the wafer and Teflon coating are heated under vacuum at 220 C for one hour in order to drive off any residual solvent present in the composite film. After this, a second blank, glass wafer is brought down from above and the stack is held under vacuum at 3 atm mechanical pressure for ten 10 hours.

Willis, Peter↗

NASA NTRS2010

Simple Check Valves for Microfluidic Devices

A simple design concept for check valves has been adopted for microfluidic devices that consist mostly of (1) deformable fluorocarbon polymer membranes sandwiched between (2) borosilicate float glass wafers into which channels, valve seats, and holes have been etched. The first microfluidic devices in which these check valves are intended to be used are micro-capillary electrophoresis (microCE) devices undergoing development for use on Mars in detecting compounds indicative of life. In this application, it will be necessary to store some liquid samples in reservoirs in the devices for subsequent laboratory analysis, and check valves are needed to prevent cross-contamination of the samples. The simple check-valve design concept is also applicable to other microfluidic devices and to fluidic devices in general. These check valves are simplified microscopic versions of conventional rubber- flap check valves that are parts of numerous industrial and consumer products. These check valves are fabricated, not as separate components, but as integral parts of microfluidic devices. A check valve according to this concept consists of suitably shaped portions of a deformable membrane and the two glass wafers between which the membrane is sandwiched (see figure). The valve flap is formed by making an approximately semicircular cut in the membrane. The flap is centered over a hole in the lower glass wafer, through which hole the liquid in question is intended to flow upward into a wider hole, channel, or reservoir in the upper glass wafer. The radius of the cut exceeds the radius of the hole by an amount large enough to prevent settling of the flap into the hole. As in a conventional rubber-flap check valve, back pressure in the liquid pushes the flap against the valve seat (in this case, the valve seat is the adjacent surface of the lower glass wafer), thereby forming a seal that prevents backflow.

Willis, Peter A.↗

NASA NTRS2013

Fabrication Methods for Adaptive Deformable Mirrors

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Toda, Risaku↗

NASA NTRS2016

Double Sided Si(Ge)/Sapphire/III-Nitride Hybrid Structure

One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic <111> direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.

Park, Yeonjoon↗

NASA NTRS2017

Method of Fabricating Double Sided Si(Ge)/Sapphire/III-Nitride Hybrid Structure

Park, Yeonjoon↗

NASA NTRSDate not supplied

Study of Fallout Metrics for Contamination Analysis

A challenge present in assessing contamination accumulation on many missions is predicting fallout during ground processing given the multiple and various orientations possible for surfaces such as optics and instruments. The best practice assumption has been to quantify particle build up on vertical surfaces as approximately 1/10 that of horizontal surfaces. This fractional relation is important when considering contamination allocations necessary to meet cleanliness requirements since spacecraft can be in many orientations during integration and testing. There is insufficient data to provide confidence in the 1/10 approximation, yet its use can have a significant effect on mission end of life contamination level predictions, leading to expenditures of precious resources to meet mission requirements. A study was conducted to compare and analyze the fallout in horizontal and vertical orientations. Silicon wafers were deployed in four different facilities. Data sets from a long term deployment of wafers were analyzed from a cleanroom facility housing integration of the James Webb Space Telescope (JWST) as well as from a shorter term deployment of wafers in three cleanroom facilities at Goddard Space Flight Center with lower activity. There are many variables influencing the relationship between fallout on vertical and horizontal wafers, including wafer position with respect to air flow, air changes in the facility, duration of exposure, and activity workload. The goal of this continuing study is to develop a tool to inform particulate accumulation predictions for future projects.

Contamination↗

DOE OSTI2023

Water production for coffee brewing by electrodeionization

A resin-wafer electrodeionization (RW-EDI) apparatus for purifying water for coffee brewing comprises a cathode; an anode; and multiple porous solid resin wafer exchange units arranged in a stack between the cathode and the anode, and an air distributor adapted and arranged to aerate the water to be purified. Each unit comprises a monovalent cation exchange membrane (CEM), an anion exchange membrane (AEM), and an ion exchange resin wafer between the CEM and the AEM, which is in contact with, and in fluid flow connection with the CEM and AEM. Each resin wafer comprises a cation exchange resin and an anion exchange resin. The units are oriented with the CEM facing the cathode and the AEM facing the anode, with space between the units defining ion concentrate chambers. Bipolar ion exchange membranes separate the anode and cathode from their nearest resin wafer exchange units.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

DOE OSTI2020

Performance of Al-Mn Transition-Edge Sensor Bolometers in SPT-3G

SPT-3G is a polarization-sensitive receiver, installed on the South Pole Telescope, that measures the anisotropy of the cosmic microwave background (CMB) from degree to arcminute scales. The receiver consists of ten 150-mm-diameter detector wafers, containing a total of similar to 16,000transition-edge sensor (TES) bolometers observing at 95, 150, and 220 GHz. During the 2018-2019 austral summer, one of these detector wafers was replaced by a new wafer fabricated with Al-Mn TESs instead of the Ti/Au design originally deployed for SPT-3G. We present the results of in-laboratory characterization and on-sky performance of this Al-Mn wafer, including electrical and thermal properties, optical efficiency measurements, and noise-equivalent temperature. In addition, we discuss and account for several calibration-related systematic errors that affect measurements made using frequency-domain multiplexing readout electronics.

Al-Mn↗

DOE OSTI2020

Commercially Fabricated Antenna-Coupled Transition Edge Sensor Bolometer Detectors for Next-Generation Cosmic Microwave Background Polarimetry Experiment

We report on the development of commercially fabricated multi-chronic antenna-coupled transition edge sensor (TES) bolometer arrays for cosmic microwave background (CMB) polarimetry experiments. The orders of magnitude increase in detector count for next-generation CMB experiments require a new approach in detector wafer production to increase fabrication throughput. Here, we describe collaborative efforts with a commercial superconductor electronics fabrication facility (SeeQC, Inc.) to fabricate antenna-coupled TES bolometer detectors. We have successfully fabricated an operational dual-polarization, dichroic sinuous antenna-coupled TES detector array on a 150-mm-diameter wafer. The fabricated detector arrays have average yield of 95% and excellent uniformity across the wafer. Both RF characteristics and TES bolometer properties are suitable for CMB observations. We successfully fabricated different types of TES bolometers optimized for frequency multiplexing readout, time-domain multiplexing readout, and microwave SQUID multiplexing readout. We also demonstrated high production throughput. We discuss the motivation, design considerations, fabrication processes, test results, and how industrial detector fabrication could be a path to fabricate hundreds of detector wafers for future CMB polarimetry experiments.

47 OTHER INSTRUMENTATION↗