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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Temperature and illumination dependence of silicon heterojunction solar cells with a wide range of wafer resistivities

Abstract Recently, the significant improvements in the surface and contact passivation of silicon (Si) solar cells as well as their bulk quality have shifted their operating point to higher injections. Hence, they are less dependent on wafer doping. This shift opens an opportunity of using high‐resistivity wafers for practical photovoltaic applications, introducing a promising approach to push the cell efficiency towards the intrinsic limit and to improve the module reliability by increasing the cell breakdown voltage. Therefore, insights into the performance of Si solar cells using high‐resistivity wafers at various operating temperatures are of significant interest. In this study, we investigate the temperature‐ and illumination‐dependent performance of Si heterojunction (SHJ) solar cells using a wide range of wafer resistivities (between 3 and 1000 Ω⋅cm). Although a reduction in the passivation quality of the passivating contacts is observed at elevated temperature, the impact on the temperature coefficient of the open‐circuit voltage (TC V oc )—the dominant contributor to the temperature coefficient (TC) of the cell efficiency—is very limited. Their TC V oc are still dominated by the temperature dependence of the effective intrinsic carrier concentration. Furthermore, we also find that the investigated cells are more sensitive to temperature variation at lower illumination intensities. It is noteworthy that the efficiency of the cells fabricated using high‐resistivity wafers is comparable to that of the reference cells at any given temperature, highlighting the potential of using high‐resistivity wafers for solar cells.

14 SOLAR ENERGY↗
NASA NTRS1988

Laser furnace and method for zone refining of semiconductor wafers

A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

Griner, Donald B.↗
NASA NTRS2006

Equipment for On-Wafer Testing From 220 to 325 GHz

A system of electronic instrumentation, constituting the equivalent of a two-port vector network analyzer, has been developed for use in on-wafer measurement of key electrical characteristics of semiconductor devices at frequencies from 220 to 325 GHz. A prior system designed according to similar principles was reported in Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (NPO-20760), NASA Tech Briefs, Vol. 25, No. 11 (November 2001), page 42. As one would expect, a major source of difficulty in progressing to the present higher-frequency-range system was the need for greater mechanical precision as wavelengths shorten into the millimeter range, approaching the scale of mechanical tolerances of prior systems. The system (see figure) includes both commercial off-the-shelf and custom equipment. As in the system of the cited prior article, the equipment includes test sets that are extended versions of commercial network analyzers that function in a lower frequency range. The extension to the higher frequency range is accomplished by use of custom frequency-extension modules that contain frequency multipliers and harmonic mixers. On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an on-wafer calibration substrate designed for use with these probes. In this case, the calibration substrate was specially fabricated by laser milling. The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz. Some of the measurement results showed that the device had gain.

Samoska, Lorene↗
NASA NTRS2013

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Allton, Judith H.↗
NASA NTRS2017

X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

Park, Yeonjoon↗
DOE OSTI2023

Wafer-Scale Synthesis of 2D Materials by an Amorphous Phase-Mediated Crystallization Approach

The interest in the wafer-scale growth of two-dimensional (2D) materials, including transition metal dichalcogenides (TMDCs), has been rising for transitioning from lab-scale devices to commercial-scale systems. Among various synthesis techniques, physical vapor deposition, such as pulsed laser deposition (PLD), has shown promise for the wafer-scale growth of 2D materials. However, due to the high volatility of chalcogen atoms (e.g., S and Se), films deposited by PLD usually suffer from a lack of stoichiometry and chalcogen deficiency. To mitigate this issue, excess chalcogen is necessary during the deposition, which results in problems like uniformity or not being repeatable. This study demonstrates a condensed-phase or amorphous phase-mediated crystallization (APMC) approach for the wafer-scale synthesis of 2D materials. This method uses a room-temperature PLD process for the deposition and formation of amorphous precursors with controlled thicknesses, followed by a post-deposition crystallization process to convert the amorphous materials to crystalline structures. This approach maintains the stoichiometry of the deposited materials throughout the deposition and crystallization process and enables the large-scale synthesis of crystalline 2D materials (e.g., MoS 2 and WSe 2 ) on Si/SiO 2 substrates, which is critical for future wafer-scale electronics. We show that the thickness of the layers can be digitally controlled by the number of laser pulses during the PLD phase. Optical spectroscopy is used to monitor the crystallization dynamics of amorphous layers as a function of annealing temperature. The crystalline quality, domain sizes, and the number of layers were explored using nanoscale and atomistic characterization (e.g., AFM, STEM, and EDS) along with electrical characterization to explore process–structure–performance relationships. Finally, this growth technique is a promising method that could potentially be adopted in conventional semiconductor industries for wafer-scale manufacturing of next-generation electronic and optoelectronic devices.

2D electronics↗
DOE OSTI2023

High-throughput manufacturing of epitaxial membranes from a single wafer by 2D materials-based layer transfer process

Layer transfer techniques have been extensively explored for semiconductor device fabrication as a path to reduce costs and to form heterogeneously integrated devices. These techniques entail isolating epitaxial layers from an expensive donor wafer to form freestanding membranes. However, current layer transfer processes are still low-throughput and too expensive to be commercially suitable. Here we report a high-throughput layer transfer technique that can produce multiple compound semiconductor membranes from a single wafer. We directly grow two-dimensional (2D) materials on III–N and III–V substrates using epitaxy tools, which enables a scheme comprised of multiple alternating layers of 2D materials and epilayers that can be formed by a single growth run. Each epilayer in the multistack structure is then harvested by layer-by-layer mechanical exfoliation, producing multiple freestanding membranes from a single wafer without involving time-consuming processes such as sacrificial layer etching or wafer polishing. Moreover, atomic-precision exfoliation at the 2D interface allows for the recycling of the wafers for subsequent membrane production, with the potential for greatly reducing the manufacturing cost.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2025

Wafer-Free Crystalline Silicon Solar Cells (CRADA Final Report)

This CRADA project, based on the DOE Solar Energy Technologies Office (SETO) Solar Prize Voucher program, helped Leap Photovoltaics to develop methodologies to immobilize Si particles by permanently attaching them to an Al-coated substrate and thereby forming carrier-selective electrical contacts to the Si particles. The bigger goal was to help Leap Photovoltaics develop these immobilized and contacted particle arrays into relatively efficient, inexpensive, and industrially relevant solar cells. By using Si particles instead of wafers in a solar cell absorber layer, one can avoid costs associated with growing monocrystalline Si ingots, then diamond-sawing them into wafers, then processing wafers into cells – a mainstream practice in today's high-efficiency Si cell and module technology. Monocrystalline or polycrystalline Si particles can be obtained in various ways: for example, Si kerf from wafer sawing is monocrystalline; recycled Si cell wafers can be ball-milled into particles; particles can be grown using various gas-phase techniques (mostly from SiH4). These Si particles can be assembled onto a substrate and serve as an absorber layer for the solar cell, absorbing photons to generate photocarriers. The challenge with this technique is to collect photocarriers from individual Si particles, with separation of photogenerated electrons to the negative cell’s electrode and positive photogenerated holes to the positive electrode. Therefore, each particle must have two isolated, carrier-selective contacts: one for electrons and one for holes. Plus, particles need to be immobilized onto a solid substrate. The goal of this work was focused on the immobilization of Si particles and creating hole-selective contact to them at the same time, using industrially relevant Si photovoltaic (PV) cell technology: screen printing of Al back-surface field electrodes. This is used in the mainstream Propane Education and Research Council (PERC) technology for hole-collecting contacts at the back of the cell. The work performed at NREL consisted of screen printing of Al metal paste on substrates, spreading Si particles onto it, and thermally processing the structures to form hole-collecting contacts. The final structures were investigated by scanning electron microscopy (SEM) after focused ion beam (FIB) cross-sectioning and polishing. The work was done jointly by NREL staff and Leap Photovoltaics (Leap PV) employees stationed at NREL. The samples were then taken to Leap PV for further processing. Training the Leap PV employee on various NREL techniques (laser cutting, screen printing, thermal processing, characterization) was part of the scope.

14 SOLAR ENERGY↗
NASA NTRS1982

ID wafering technology

Improvements in ID saws leading to lower costs for producing silicon wafers for solar cells are described. The relationships between crystal size and blade size and between the length of time it takes to slice a wafer and wafer thickness are discussed. The influence of ingot production methods on wafering performance is considered. A cost sensitivity analysis of slicing a 10 cm square ingot and economic analyses of slicing a four inch and a six inch ingot are presented. A wafering cost model based on the IPEG 2 is given.

Aharonyan, P.↗
NASA NTRS1994

The Imaging Properties of a Silicon Wafer X-Ray Telescope

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

Joy, M. K.↗
NASA NTRS2004

Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

Simons, Rainee N.↗
DOE OSTI2024

Acoustics-based noninvasive wafer defect detection

Techniques are provided for detecting wafer defects. Example techniques include exciting a wafer using an acoustic signal to cause the wafer to exhibit vibrations, measuring one or more of linear frequency response metrics or nonlinear frequency responses metrics associated with the vibrations, and identifying any defects in the wafer based at least in part on one or more of the linear frequency response metrics or nonlinear frequency responses metrics. In embodiments, the wafer includes bismuth telluride (Bi 2 Te 3 ).

Pantea, Cristian↗
DOE OSTI2023

Integrated Ion-Exchange Membrane Resin Wafer Assemblies for Aromatic Organic Acid Separations Using Electrodeionization

Aromatic acids, such as p-coumaric acid, are valuable chemical intermediates that are used in the specialty chemical industries because they are precursors to phenylpropanoid compounds. The separation of p-coumaric acid from fermentation broths is a critical step in the biochemical production process and more broadly the circular carbon economy. Electrodeionization (EDI) has been applied toward separations of low-carbon chain acids, but purifying p-coumaric acid has been challenging due to fouling and irreversible binding with ion-exchange membranes and resins. Here, we report a new membrane wafer assembly (MWA) consisting of laminated ion exchange membranes to porous ionomer-binder resin wafers for EDI. The MWAs in an EDI stack showed a 7-fold increase in p-coumaric acid capture while also using 70% less specific energy consumption when benchmarked against state-of-the-art resin wafer EDI modules. The more efficient p-coumaric acid recovery was ascribed to (i) the 38% reduction in interfacial transport resistance between the membrane and resin wafer and (ii) using imidazolium anion exchange membranes and ionomer binders in the MWA. MD simulations revealed enhanced transport rates for p-coumarate in imidazolium ionomers through π–π interactions. As a result, adopting the new MWA significantly reduced the amount of ion-exchange membranes in EDI and may lead to drastic capital cost savings.

42 ENGINEERING↗
DOE OSTI2022

Generation of selective single-mode guided waves by d 36 type piezoelectric wafer

In general, mixed modes and dispersion of guided wave occur at any excitation frequency, while single modes are needed for effective nondestructive evaluation of structures. In this work, we present an approach to generate a selective single-mode guided wave in plate-like structures by exploiting the unique directionality of the d 36 type piezoelectric wafer and the symmetry of fundamental guided wave modes. Specifically, we devise a unified fundamental shear horizontal (SH 0 ) wave/fundamental antisymmetric mode (A 0 ) wave directional transducer pair by attaching the d 36 type piezoelectric wafers back to back on the opposite sides of the plate to provide selective, directional single-mode guided waves for actuation and sensing. Originally, the d 36 -type piezoelectric wafer, poled and cut from the lead magnesium niobate-lead titanate crystal, produces a mixture of the in-plane SH 0 (symmetric) mode and out-of-plane A 0 (asymmetric) and S 0 (symmetric) modes. By applying the in-phase or out-of-phase applied electrical field to the coupled d 36 -type piezoelectric wafer pair, our devised approach generates selective single modes, SH 0 or A 0 , respectively, to propagate in the structure. We describe the theoretical development of our approach and conduct both numerical simulations and laboratory experiments for validations.

42 ENGINEERING↗
DOE OSTI2023

Nature of contaminants introduced in silicon wafers during molecular beam epitaxy chamber annealing

Epitaxial monolithic III–V/Si tandem solar cells are one of the most promising technologies to be adopted by the industry after the efficiency of the current market dominating single junction silicon solar cell saturates at its fundamental limit. One of the key limitations of this technology is the degradation of silicon wafers during in situ annealing in the molecular beam epitaxy chamber. Determining the nature of contaminants in this process is key to improve the efficiency of epitaxial tandem solar cells. However, to date, the nature of contaminants from molecular beam epitaxy chambers remains unknown. In this work, we use photoluminescence imaging, lifetime spectroscopy, and deep level transient spectroscopy to measure the electronic properties of extrinsic impurities incorporated during annealing in the molecular beam epitaxy chamber. Photoluminescence images reveal that at least two impurities diffuse into silicon wafers during molecular beam epitaxy annealing. One is highly localized, while the other one is distributed uniformly across the whole wafer. Phosphorus diffusion is found to confine the localized impurity within the diffused layer but is ineffective at preventing the indiffusion of other impurities. Lifetime spectroscopy shows that metastable impurities with characteristic similar to Cr and CrB in our molecular beam epitaxy annealed silicon wafers. No evidence of Fe or FeB was observed. The emission rates and concentrations of the electrically active defects were measured with deep-level transient spectroscopy: The emission rates of detected defects do not match that of known Cr-related defects.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Specifications and pre-production of n + -in-p large-format strip sensors fabricated in 6-inch silicon wafers, ATLAS18, for the Inner Tracker of the ATLAS Detector for High-Luminosity Large Hadron Collider

Abstract The ATLAS experiment is constructing new all-silicon inner tracking system for HL-LHC. The strip detectors cover the radial extent of 40 to 100 cm. A new approach is adopted to use p-type silicon material, making the readout in n + -strips, so-called n + -in-p sensors. This allows for enhanced radiation tolerance against an order of magnitude higher particle fluence compared to the LHC. To cope with varying hit rates and occupancies as a function of radial distance, there are two barrel sensor types, the short strips (SS) for the inner 2 and the long strips (LS) for the outer 2 barrel cylinders, respectively. The barrel sensors exhibit a square, 9.8 × 9.8 cm 2 , geometry, the largest possible sensor area from a 6-inch wafer. The strips are laid out in parallel with a strip pitch of 75.5 μm and 4 or 2 rows of strip segments. The strips are AC-coupled and biased via polysilicon resistors. The endcap sensors employ a “stereo-annulus” geometry exhibiting a skewed-trapezoid shapes with circular edges. They are designed in 6 unique shapes, R0 to R5, corresponding to progressively increasing radial extents and which allows them to fit within the petal geometry and the 6-inch wafer maximally. The strips are in fan-out geometry with an in-built rotation angle, with a mean pitch of approximately 75 μm and 4 or 2 rows of strip segments. The eight sensor types are labeled as ATLAS18xx where xx stands for SS, LS, and R0 to R5. According to the mechanical and electrical specifications, CAD files for wafer processing were laid out, following the successful designs of prototype barrel and endcap sensors, together with a number of optimizations. A pre-production was carried out prior to the full production of the wafers. The quality of the sensors is reviewed and judged excellent through the test results carried out by vendor. These sensors are used for establishing acceptance procedures and to evaluate their performance in the ATLAS collaboration, and subsequently for pre-production of strip modules and stave and petal structures.

Instruments & Instrumentation↗
DOE OSTI2025

Wafer-scale waveguide sidewall roughness scattering loss characterization by image processing

Photonic integrated circuits (PICs) are vital for developing affordable, high-performance optoelectronic devices that can be manufactured at an industrial scale, driving innovation and efficiency in various applications. Optical loss of modes in thin film waveguides and devices is a critical measure of their performance. Thin film growth, lithography, masking, and etching processes are imperfect processes that introduce significant sidewall and top-surface roughness and cause dominating optical losses in waveguides and photonic structures. This roughness, as perturbations couple light from guided to far-field radiation modes, leads to scattering losses that can be estimated from theoretical models. Typically, with UV-based lithography, sidewall roughness is significantly larger than wafer-top surface roughness. Atomic force microscopy (AFM) imaging measurement gives a 3D and high-resolution roughness profile, but the measurement is inconvenient, costly, and unscalable for large-scale PICs and at wafer-scale. Here, we evaluate the sidewall roughness profile based on 2D high-resolution scanning electron microscope (SEM) imaging. We characterized the loss on two homemade nitride and oxide films on 3-inch silicon wafers with 12 waveguide devices on each and correlated the scattering loss estimated from a 2D image-based sidewall profile and theoretical Payne model. The lowest loss of guided fundamental transverse electric (TE 0 ) mode is found at 0.075 dB/cm at 633 nm across 24 devices, a record at visible wavelength. Our work shows 100% success (edge continuity span exceeding 95% of image width/height) in edge detection in image processing of all images to estimate autocorrelation function and optical mode loss. These demonstrations offer valuable insights into waveguide sidewall roughness and a comparison of experimental and 2D SEM image processing based loss estimations with applications in loss characterization at wafer-scale PICs.

Khurana, Mohit (ORCID:0000000207898672)↗
DOE OSTI2022

Excess carrier concentration in silicon devices and wafers: How bulk properties are expected to accelerate light and elevated temperature degradation

Light and elevated temperature induced degradation (LeTID) is accelerated nearly linearly by the presence of excess carriers. It is therefore important to understand how excess carrier concentration (Δn) changes as a function of exposure conditions, materials properties, and sample structure. We simulate Δn as a function of wafer thickness and bulk minority carrier lifetime (τ) in solar cells and wafers using SCAPS and Quokka3. We also derive closed-form analytic expressions. For wafers, there is a near-linear relationship between Δn and τ or thickness, whereas for solar cells, Δn in the bulk may become limited by rear surface recombination. Thus, LeTID may progress more quickly in wafers than in cells, with a stronger dependence on τ. When comparing experiments, observed degradation rates must be corrected between samples or conditions to account for differences in Δn. This study demonstrates three tools to estimate the magnitude of such corrections, which can aid in the quantitative interpretation of LeTID data and performance predictions. Finally, while each tool yields similar results, there are advantages to each approach that must be weighed in terms of simplicity of inputs versus sophistication of treatment. Incomplete specification of back contact characteristics in commercial products is identified as an important contributor to uncertainty in expected LeTID rates.

36 MATERIALS SCIENCE↗