Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “transistors”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2016

Fabrication and characterization of p{sup +}-i-p{sup +} type organic thin film transistors with electrodes of highly doped polymer

Organic thin film transistors (OTFTs) have been explored because of their advantageous features such as light-weight, flexible, and large-area. For more practical application of organic electronic devices, it is very important to realize OTFTs that are composed only of organic materials. In this paper, we have fabricated p{sup +}-i-p{sup +} type of OTFTs in which an intrinsic (i) regioregular poly (3-hexylthiophene) (P3HT) layer is used as the active layer and highly doped p-type (p{sup +}) P3HT is used as the source and drain electrodes. The 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F{sub 4}-TCNQ) was used as the p-type dopant. A fabricating method of p{sup +}-i-p{sup +} OTFTs has been developed by using SiO{sub 2} and aluminum films as capping layers for micro-scaled patterning of the p{sup +}-P3HT electrodes. The characteristics of the OTFTs were examined using the photoelectron spectroscopy and electrical measurements. We demonstrated that the fabricated p{sup +}-i-p{sup +} OTFTs work with carrier injection through a built-in potential at p{sup +}/i interfaces. We found that the p{sup +}-i-p{sup +} OTFTs exhibit better FET characteristics than the conventional P3HT-OTFT with metal (Au) electrodes, indicating that the influence of a carrier injection barrier at the interface between the electrode and the active layer was suppressed by replacing the metal electrodes with p{sup +}-P3HT layers.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

An AlN/Al 0.85 Ga 0.15 N high electron mobility transistor

An AlN barrier high electron mobility transistor (HEMT) based on the AlN/Al 0.85 Ga 0.15 N heterostructure was grown, fabricated, and electrically characterized, thereby extending the range of Al composition and bandgap for AlGaN channel HEMTs. An etch and regrowth procedure was implemented for source and drain contact formation. A breakdown voltage of 810 V was achieved without a gate insulator or field plate. Excellent gate leakage characteristics enabled a high I on /I off current ratio greater than 10 7 and an excellent subthreshold slope of 75 mV/decade. A large Schottky barrier height of 1.74 eV contributed to these results. In conclusion, the room temperature voltage-dependent 3-terminal off-state drain current was adequately modeled with Frenkel-Poole emission.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2017

Interfacial Charge Engineering in Ferroelectric-Controlled Mott Transistors

Heteroepitaxial coupling at complex oxide interfaces introduces a powerful tool for engineering the charge degree of freedom in strongly correlated materials, which can be utilized to achieve tailored functionalities that are inaccessible in the bulk form. In this work, the charge-transfer effect between two strongly correlated oxides, Sm 0.5 Nd 0.5 NiO 3 (SNNO) and La 0.67 Sr 0.33 MnO 3 (LSMO), is exploited to realize a giant enhancement of the ferroelectric field effect in a prototype Mott field-effect transistor. By switching the polarization field of a ferroelectric Pb(Zr,Ti)O 3 (PZT) gate, nonvolatile resistance modulation in the Mott transistors with single-layer SNNO and bilayer SNNO/LSMO channels is induced. For the same channel thickness, the bilayer channels exhibit up to two orders of magnitude higher resistance-switching ratio at 300 K, which is attributed to the intricate interplay between the charge screening at the PZT/SNNO interface and the charge transfer at the SNNO/LSMO interface. X-ray absorption spectroscopy and X-ray photoelectron spectroscopy studies of SNNO/LSMO heterostructures reveal about 0.1 electron per 2D unit cell transferred between the interfacial Mn and Ni layers, which is corroborated by first-principles density functional theory calculations. The study points to an effective strategy to design functional complex oxide interfaces for developing high-performance nanoelectronic and spintronic applications.

36 MATERIALS SCIENCE↗
NASA NTRS1972

Complementary transistor-transistor logic /CTTL/ - An approach to high-speed micropower logic.

Description of a new approach to micropower integrated circuits that is called complementary transistor-transistor logic (CTTL). This logic combines the inherent low standby power of a complementary inverter with the high speed of the TTL-type input. Results of monolithic fabricated circuits are presented. These circuits are shown to be equally adaptable to hybrid and discrete circuitry.

Stehlin, R. A.↗
DOE OSTI2018

Thick Layered Semiconductor Devices with Water Top-Gates: High On–Off Ratio Field-Effect Transistors and Aqueous Sensors

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore deionized (DI) water as a solution top-gate for field-effect switching of layered semiconductors including SnS 2 , MoS 2 , and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on–off current ratios, near-ideal subthreshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels, where such control is difficult to realize with conventional back gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. In conclusion, DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Gate-modulated conductance of few-layer WSe{sub 2} field-effect transistors in the subgap regime: Schottky barrier transistor and subgap impurity states

Two key subjects stand out in the pursuit of semiconductor research: material quality and contact technology. The fledging field of atomically thin transition metal dichalcogenides (TMDCs) faces a number of challenges in both efforts. This work attempts to establish a connection between the two by examining the gate-dependent conductance of few-layer (1-5L) WSe{sub 2} field effect devices. Measurements and modeling of the subgap regime reveal Schottky barrier transistor behavior. We show that transmission through the contact barrier is dominated by thermionic field emission (TFE) at room temperature, despite the lack of intentional doping. The TFE process arises due to a large number of subgap impurity states, the presence of which also leads to high mobility edge carrier densities. The density of states of such impurity states is self-consistently determined to be approximately 1–2 × 10{sup 13}/cm{sup 2}/eV in our devices. We demonstrate that substrate is unlikely to be a major source of the impurity states and suspect that lattice defects within the material itself are primarily responsible. Our experiments provide key information to advance the quality and understanding of TMDC materials and electrical devices.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2016

Ab-initio simulations of higher Miller index Si:SiO{sub 2} interfaces for fin field effect transistor and nanowire transistors

Models of three representative higher Miller index interfaces, Si(310):SiO{sub 2}, Si(410):SiO{sub 2}, and Si(331):SiO{sub 2}, have been built by an ab-initio molecular dynamics method. We show that each interface can be made as a fully bonded network without any defects and has a reasonable electronic structure for use in fin field effect transistors or gate-all-around nanowire devices. The differences in numbers of oxygen bridges are attributed to the intermediate sub-oxide components and the atomic step structure. The interface bonding schemes to passivate different densities of dangling bonds on different facets are also analyzed.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2017

Stochastic Gain Degradation in III-V Heterojunction Bipolar Transistors due to Single Particle Displacement Damage

As device dimensions decrease single displacement effects are becoming more important. We measured the gain degradation in III-V Heterojunction Bipolar Transistors due to single particles using a heavy ion microbeam. Two devices with different sizes were irradiated with various ion species ranging from oxygen to gold to study the effect of the irradiation ion mass on the gain change. From the single steps in the inverse gain (which is proportional to the number of defects) we calculated Cumulative Distribution Functions to help determine design margins. The displacement process was modeled using the Marlowe Binary Collision Approximation (BCA) code. The entire structure of the device was modeled and the defects in the base-emitter junction were counted to be compared to the experimental results. While we found good agreement for the large device, we had to modify our model to reach reasonable agreement for the small device.

42 ENGINEERING↗
DOE OSTI2019

Photo‐/Thermal‐Responsive Field‐Effect Transistor upon Blending Polymeric Semiconductor with Hexaarylbiimidazole toward Photonically Programmable and Thermally Erasable Memory Device

Abstract It is shown that the semiconducting performance of field‐effect transistors (FETs) with PDPP4T (poly(diketopyrrolopyrrole‐quaterthiophene)) can be reversibly tuned by UV light irradiation and thermal heating after blending with the photochromic hexaarylbiimidazole compound ( p ‐NO 2 ‐HABI). A photo‐/thermal‐responsive FET with a blend thin film of PDPP4T and p ‐NO 2 ‐HABI is successfully fabricated. The transfer characteristics are altered significantly with current enhanced up to 10 6 ‐fold at V G = 0 V after UV light irradiation. However, further heating results in the recovery of the transfer curve. This approach can be extended to other semiconducting polymers such as P3HT (poly(3‐hexyl thiophene)), PBTTT (poly(2,5‐bis(3‐tetradecylthiophen‐2‐yl)thieno[3,2‐b] thiophene)) and PDPPDTT (poly(diketopyrrolopyrrole‐dithienothiophene)). It is hypothesized that TPIRs (2,4,5‐triphenylimidazolyl radicals) formed from p ‐NO 2 ‐HABI after UV light irradiation can interact with charge defects at the gate dielectric–semiconductor interface and those in the semiconducting layer to induce more hole carriers in the semiconducting channel. The application of the blend thin film of PDPP4T and p ‐NO 2 ‐HABI is further demonstrated to fabricate the photonically programmable and thermally erasable FET‐based nonvolatile memory devices that are advantageous in terms of i) high ON/OFF current ratio, ii) nondestructive reading at low electrical bias, and iii) reasonably highly stable ON‐state and OFF‐state.

Liu, Yidong↗
DOE OSTI2018

Highly Contrasting Static Charging and Bias Stress Effects in Pentacene Transistors with Polystyrene Heterostructures Incorporating Oxidizable N , N '-Bis(4-methoxyphenyl)aniline Side Chains as Gate Dielectrics

Charge storage and trapping properties of polymer dielectrics govern the charge densities of adjacent semiconductors and greatly influence the on-off switching voltage (threshold voltage, V th ) of organic field-effect transistors (OFETs) when the polymers are used as gate insulators. Intentional charging of polymer dielectrics in OFETs can change V th and affect the bias stress. We describe a chemical design and fabrication protocol to construct multilayer-stack dielectrics for pentacene-based OFETs using different polystyrene (PS)-based polymers in each layer, with oxidizable N,N-bis(4-methoxyphenyl)anilino (TPAOMe)-substituted styrene copolymers in arbitrary vertical positions in the stacks. Thermal, byproduct-free crosslinking of benzocyclobutene subunits provides integrity to the multilayer structure by preventing dissolution of the previous deposited layer. Neutron reflectivity data verified the multilayer morphology. We compared the Vth shift before and after charging the stacks by application of ±100V across 0.5-1 µm total film thicknesses. Bias stress was the dominant effect in bilayer devices with a TPAOMe layer in contact with the pentacene, indicated by the direction of V th shift associated with either polarity of external electric field. In structures with no TPAOMe subunit in contact with the pentacene, when charging with -100V on top of the source and drain electrodes, electron injection from pentacene to dielectric was the major charging mechanism, again consistent with the bias stress direction. When charging with +100V, bilayer devices without TPAOMe showed little change in V th , suggesting there was no bias stress effect or charge injection in these devices for this charging polarity. For the bilayer devices with the TPAOMe layer in the bottom, and the trilayer devices with TPOMe in the middle, when +100V was applied, the V th shifts were opposite those expected from bias stress. Dipole formation or partial ionization of chargeable groups at the interface between the dielectric layers are likely polarization mechanisms in these cases. A simple analytical model supports the plausibility of these mechanisms. This work provides examples of both stabilization and shifting of V th , and therefore controlling charge carrier density, in semiconductors overlying the dielectric multilayers.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2015

The fundamental downscaling limit of field effect transistors

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗