Components irradiation test no. 15 - 2N708, 2N918, S2N1486 and S2N2412 transistors and 2N2498 field effect transistor
Neutron and gamma radiation effects on field effect transistor and injection transistors
RADIATION EFFECT↗
SEARCH · Engineering Papers
Results for “transistors”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Complementary transistor-transistor logic /CTTL/ - An approach to high-speed micropower logic.
Description of a new approach to micropower integrated circuits that is called complementary transistor-transistor logic (CTTL). This logic combines the inherent low standby power of a complementary inverter with the high speed of the TTL-type input. Results of monolithic fabricated circuits are presented. These circuits are shown to be equally adaptable to hybrid and discrete circuitry.
Stehlin, R. A.↗
Metal Oxide Semiconductor /MOS/ transistor research and development program. Part II - Development of stable complementary MOS FIELD effect transistors Final report, Mar. - Nov. 1965
Simultaneous fabrication of enhancement mode metal oxide semiconductor transistors in epitaxial material
TRANSISTOR↗
Impact of 12-nm FinFET Technology Variations on TID Effects: A Comparative Study of GF 12LP and 12LP+ at the Transistor Level
Here, this article presents a comparative analysis of total ionizing dose (TID) response in GlobalFoundries’ (GF) 12 low-power (LP) and 12LP+12-nm bulk fin field effect transistor (FinFET) technologies using 10-keV X-rays. Our findings show that 12LP+ n-type transistors demonstrate higher sensitivity to TID degradation of the off-state leakage drain current compared to 12LP. Data indicate that for both 12LP and 12LP+, transistors with higher threshold voltages (VTs) exhibit lower off-state drain-source leakage postirradiation compared to transistors with lower VTs. Data consistently show that transistors with fewer fins per transistor show superior TID tolerance, in both 12LP and 12LP+ technologies. Lower VT transistors in both technologies display similar preirradiation leakage currents. On the other hand, higher VT transistors in 12LP+ show lower preirradiation leakage currents than those in 12LP, highlighting that the front-end-of-line of 12LP+ technology has been modified compared to 12LP. p-type devices in 12LP+ presented negligible degradation. Larger TID sensitivity in 12LP+ might be attributed to the implementation of dual-metal gate work functions, reduced halo doping, deeper source/drain (S/D) doping profiles, and/or 12LP+ having narrower fins compared to 12LP.
Dual-metal gate work functions↗
Efficient and Robust p-Type Transistor Based on Ultrawide-Bandgap Semiconductor
The p-type transistor is an indispensable component of semiconductor technology, enabling a complementary operation with n-channel transistors for computation, storage, and communication. Achieving both high robustness and high efficiency is highly desirable but challenging for p-type transistors due to the limited semiconductors with reliable hole transport and their high activation energies. Here, in this study, we achieved a robust yet efficient p-type transistor by heterogeneously integrating an ultrawide-bandgap semiconductor and a high-κ dielectric layer through van der Waals integration. The p-type transistor employs a two-dimensional hole channel on hydrogenated diamond (bandgap 5.6 eV) combined with a high-κ (30.5) SrTiO 3 perovskite membrane. At room temperature, the transistor exhibits stable operation with a high on-current (∼200 mA/mm), low subthreshold swing (70 mV/dec), high hole mobility (566 cm 2 /(V·s) to 572 cm 2 /(V·s)), and high on–off ratio (∼10 9 ). Furthermore, tuning the annealing temperature allows operation in either enhancement or depletion mode. The robust p-type transistor with high efficiency holds great potential for future power electronics, ultraviolet (UV) optoelectronics, and harsh-environment electronic applications.
high-κ membrane↗
Reducing the Barrier Height in Organic Transistors
Abstract Reducing the Schottky barrier height and Fermi level de‐pinning in metal‐organic semiconductor contacts are crucial for enhancing the performance of organic transistors. The reduction of the Schottky barrier height in bottom‐contact top‐gate organic transistors is demonstrated by adding 1 nm thick atomic layer deposited Al 2 O 3 on the source and drain contacts. By using two different donor‐acceptor copolymers, both p‐ and n‐ type transistors are investigated. Temperature‐dependent current–voltage measurements from non‐treated, self‐assembled monolayer treated, and Al 2 O 3 treated Au source‐drain contact field‐effect transistors with varying channel lengths are carried out. The drain current versus drain voltage near zero gate voltage, which may be described by the thermionic emission model at temperatures above 150 K, allows the estimation of the Schottky barrier height ( φ B ). The Al 2 O 3 contact‐treated transistors show more than 40% lower φ B compared with the non‐treated contacts in the p ‐type transistor. Similarly, an isoindigo‐based transistor, with n ‐type transport, shows a reduction in φ B with Al 2 O 3 treated contacts suggesting that such ultrathin oxide layers provide a universal method for reducing the barrier height.
Ghobadi, Arash↗
High-Power, High-Frequency Si-Based (SiGe) Transistors Developed
Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.
Ponchak, George E.↗
Gyrator employing field effect transistors
A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 deg phase reversal is examined. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.
Hochmair, E. S.↗
Preventing Simultaneous Conduction In Switching Transistors
High voltage spikes and electromagnetic interference suppressed. Power-supply circuit including two switching transistors easily modified to prevent simultaneous conduction by both transistors during switching intervals. Diode connected between collector of each transistor and driving circuit for opposite transistor suppresses driving signal to transistor being turned on until transistor being turned off ceases to carry current.
Mclyman, William T.↗
Evolvable circuit with transistor-level reconfigurability
An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor terminal to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.
Stoica, Adrian↗
Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures
Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.
Patterson, Richard↗
Gate-All-Around Nanowire Field-Effect Transistors: A Historical Perspective
The development of transistor architectures, evolving from 2D planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to FinFETs and then to gate-all-around nanowire (GAANW) FETs, plays a crucial role in downscaling technology nodes in the semiconductor industry. This perspective reviews the concept of MOSFETs and summarizes this historical development with particular emphasis on GAANW transistors due to their importance in next-generation technology for nodes below 3 nm. Specifically, the concept of GAANW transistors and their advantages over planar and FinFET devices for further scaling are presented, along with a discussion of their transition from early conceptual ideas to laboratory demonstrations and, ultimately, industrial adoption. Furthermore, potential solutions, such as complementary FETs (CFETs) and 2D semiconductor-based FETs, and their associated challenges for the future generation, known as the Angstrom Era, are discussed in a technological roadmap. In conclusion, this perspective may inspire both industry and academia in future research directions for realizing the Angstrom Era.
gate-all-around transistors↗
A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design
The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.
Phillips, Thomas A.↗
Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis
Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.
Phillips, Thomas A.↗
Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate
Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.
Phillips, Thomas A.↗
T-shaped emitter metal heterojunction bipolar transistors for submillimeter wave applications
We report on the development of submillimeter wave transistors at JPL. The goal of the effort is to produce advance-reliable high frequency and high power amplifiers, voltage controlled oscillators, active multipliers, and high-speed mixed-signal circuits for space borne applications. The technology in development to achieve this is based on the Indium Phosphide (InP) Heterojunction Bipolar Transistor (HBT). The HBT is well suited for high speed, high power and uniform (across wafer) performance, due to the ability to tailor the material structure that electrons traverse through by well-controlled epitaxial growth methods. InP with its compatible lattice matched alloys such as indium gallium arsenide (InGaAs) and indium aluminium arsenide (InAlAs) provides for high electron velocities and high voltage breakdown capabilities. The epitaxial methods for this material system are fairly mature, however the implementation of high performance and reliable transistors are still under development by many laboratories. Our most recently fabricated, second generation mesa HBTs at JPL have extrapolated current gain cutoff frequency (FJ of 142GHz and power gain cutoff frequency (Fm,) of approximately 160GHz. This represents a 13% and 33% improvement of Ft and F, respectively, compared to the first generation mesa HBTs [l]. Analysis based on the University of California, Santa Barbara (UCSB) device model, RF device characteristics can be significantly improved by reducing base contact resistance and base metal contact width. We will describe our effort towards increasing transistor performance and yield.
transistor↗
Mobility and threshold voltage extraction in transistors with gate-voltage-dependent contact resistance
The mobility of emerging (e.g., two-dimensional, oxide, organic) semiconductors is commonly estimated from transistor current-voltage measurements. However, such devices often experience contact gating, i.e., electric fields from the gate modulate the contact resistance during measurements, which can lead conventional extraction techniques to estimate mobility incorrectly even by a factor >2. Although this error can be minimized by measuring transistors at high gate-source bias |V gs |, this regime is often inaccessible in emerging devices that suffer from high contact resistance or early gate dielectric breakdown. Here, we propose a method of extracting mobility in transistors with gate-dependent contact resistance that does not require operation at high |V gs |, enabling accurate mobility extraction even in emerging transistors with strong contact gating. Our approach relies on updating the transfer length method (TLM) and can achieve <10% error even in regimes where conventional techniques overestimate mobility by >2×
36 MATERIALS SCIENCE↗
Investigating the Effects of Individual Neutron-Induced Defects in Bipolar Junction Transistors
Here, this study investigates neutron-induced displacement damage in Bipolar Junction Transistors (BJTs) using TCAD models informed by Deep-Level-Transient-Spectroscopy (DLTS) data. These models are calibrated and validated against experimental measurements performed at various neutron fluences. Both npn and pnp transistor configurations are studied to analyze the effects of individual traps on carrier recombination and base leakage currents. In npn transistors, deep traps (0.42 eV from the conduction band) dominate at low voltages, while shallow traps (0.17 eV from the conduction band) become prominent at higher voltages. Conversely, pnp transistors have base leakage current predominantly due to deep-level traps. The study observes a notable trend in trap density versus fluence, characterized by a linear relationship on a log-log scale. These insights into defect evolution under radiation conditions are crucial for optimizing semiconductor device reliability and performance in radiation-prone environments.
42 ENGINEERING↗