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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

Enabling Large Focal Plane Arrays through Mosaic Hybridization

We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated.

Miller, Timothy M.↗
NASA NTRS2011

Performance Comparison of Wireless Sensor Network Standard Protocols in an Aerospace Environment: ISA100.11a and ZigBee

Wireless Sensor Networks (WSNs) can provide a substantial benefit in spacecraft systems, reducing launch weight and providing unprecedented flexibility by allowing instrumentation capabilities to grow and change over time. Achieving data transport reliability on par with that of wired systems, however, can prove extremely challenging in practice. Fortunately, much progress has been made in developing standard WSN radio protocols for applications from non-critical home automation to mission-critical industrial process control. The relative performances of candidate protocols must be compared in representative aerospace environments, however, to determine their suitability for spaceflight applications. In this paper, we will present the results of a rigorous laboratory analysis of the performance of two standards-based, low power, low data rate WSN protocols: ZigBee Pro and ISA100.11a. Both are based on IEEE 802.15.4 and augment that standard's specifications to build complete, multi-hop networking stacks. ZigBee Pro targets primarily the home and office automation markets, providing an ad-hoc protocol that is computationally lightweight and easy to implement in inexpensive system-on-a-chip components. As a result of this simplicity, however, ZigBee Pro can be susceptible to radio frequency (RF) interference. ISA100.11a, on the other hand, targets the industrial process control market, providing a robust, centrally-managed protocol capable of tolerating a significant amount of RF interference. To achieve these gains, a coordinated channel hopping mechanism is employed, which entails a greater computational complexity than ZigBee and requires more sophisticated and costly hardware. To guide future aerospace deployments, we must understand how well these standards relatively perform in analog environments under expected operating conditions. Specifically, we are interested in evaluating goodput -- application level throughput -- in a representative crewed environment in the presence of varying levels of 802.11g Wi-Fi traffic. To do so, we use the NASA Johnson Space Center Wireless Habitat Testbed (WHT), a metallic, habitation-sized module designed for co-existence testing of wireless systems. In its quiescent state, the sealed WHT provides an RF-quiet environment to which we can selectively add interfering systems; it also provides a realistic level of multi-path self-interference for systems under investigation. In our test, we deploy two representative five node networks, configured in a star topology with all nodes reporting directly to a WSN gateway. Each ZigBee network WSN node is built using a Texas Instruments (TI) CC2530 system-on-a-chip radio running TI's ZigBee Pro Z-stack. Each ISA100.11a network node is built using a Nivis VersaNode 210 system-on-a-chip radio. In both cases, radios interface with TI MSP430-F5438 microcontroller implementing a common test application. Interference is provided by a D-link 802.11g Wi-Fi router transporting traffic generated using the Iperf network testing tool. For the single-channel ZigBee network, effects of both direct and indirect Wi-Fi interference are evaluated. For the channel-hopping ISA100.11a network, effects of interference from multiple Wi-Fi routers configured in non-overlapping 802.11g channels are evaluated. Our results show that, in general, the more lightweight ZigBee network performs well at low interference levels, but performance degrades as interference increases. Conversely, the more complex and costly ISA100.11a network continues to perform well as Wi-Fi interference levels increase.

Wagner, Raymond S.↗
NASA NTRS2013

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

Jung-Kubiak, Cecile↗
NASA NTRS1994

Three-Dimensional Vertical-Bloch-Line Memory System

In proposed magnetic memory system without moving parts, data is stored in stack of two-dimensional vertical-Bloch-line (VBL) memory chips or modules. System similar to one described in "Three-Dimensional Magnetic-Bubble Memory System" (NPO-18533). Each VBL module in this memory system silimar to module described in "Vertical-Bloch-Line Memory" (NPO-18467). Advantages include high storage density, high speed, nonvolatility, and insensitivity to ionizing radiation.

Katti, Romney R.↗
NASA NTRS1996

(abstract) A High Throughput 3-D Inner Product Processor

A particularily challenging image processing application is the real time scene acquisition and object discrimination. It requires spatio-temporal recognition of point and resolved objects at high speeds with parallel processing algorithms. Neural network paradigms provide fine grain parallism and, when implemented in hardware, offer orders of magnitude speed up. However, neural networks implemented on a VLSI chip are planer architectures capable of efficient processing of linear vector signals rather than 2-D images. Therefore, for processing of images, a 3-D stack of neural-net ICs receiving planar inputs and consuming minimal power are required. Details of the circuits with chip architectures will be described with need to develop ultralow-power electronics. Further, use of the architecture in a system for high-speed processing will be illustrated.

imaging parallel processing algorithms linear vect↗
NASA NTRS2015

High Frequency Design Considerations for the Large Detector Number and Small Form Factor Dual Electron Spectrometer of the Fast Plasma Investigation on NASA's Magnetospheric Multiscale Mission

Each half of the Dual Electron Spectrometer (DES) of the Fast Plasma Investigation (FPI) on NASA's Magnetospheric MultiScale (MMS) mission utilizes a microchannel plate Chevron stack feeding 16 separate detection channels each with a dedicated anode and amplifier/discriminator chip. The desire to detect events on a single channel with a temporal spacing of 100 ns and a fixed dead-time drove our decision to use an amplifier/discriminator with a very fast (GHz class) front end. Since the inherent frequency response of each pulse in the output of the DES microchannel plate system also has frequency components above a GHz, this produced a number of design constraints not normally expected in electronic systems operating at peak speeds of 10 MHz. Additional constraints are imposed by the geometry of the instrument requiring all 16 channels along with each anode and amplifier/discriminator to be packaged in a relatively small space. We developed an electrical model for board level interactions between the detector channels to allow us to design a board topology which gave us the best detection sensitivity and lowest channel to channel crosstalk. The amplifier/discriminator output was designed to prevent the outputs from one channel from producing triggers on the inputs of other channels. A number of Radio Frequency design techniques were then applied to prevent signals from other subsystems (e.g. the high voltage power supply, command and data handling board, and Ultraviolet stimulation for the MCP) from generating false events. These techniques enabled us to operate the board at its highest sensitivity when operated in isolation and at very high sensitivity when placed into the overall system.

Microchannel plates high frequency performance↗
NASA NTRS2010

Evaluation of 3D Plus Packaging Test Structures for NASA Goddard Space Flight Center

Environmental tests were performed on packaging test structures designed and manufactured for ESA and CNES by 3D PLus ELectronics. The design provided circuit elements that acted as thermal, mechanical and moisture sensors. Other design features showed the compatibility of the packaging with chip passives, bare electronic dice and plastic encapsulated microcircuits packaged together in an innovative, stacked multichip module. The NASA GSFC testing augmented long duration testing on the same units carried out by ESA and CNES. The NASA portion demonstrated packaging stability over temperature, in moisture, with voltage stress, in shock and in vibration environments.

Plante, Jeannette↗
NASA NTRS2002

Bioinspired engineering of exploration systems for NASA and DoD

A new approach called bioinspired engineering of exploration systems (BEES) and its value for solving pressing NASA and DoD needs are described. Insects (for example honeybees and dragonflies) cope remarkably well with their world, despite possessing a brain containing less than 0.01% as many neurons as the human brain. Although most insects have immobile eyes with fixed focus optics and lack stereo vision, they use a number of ingenious, computationally simple strategies for perceiving their world in three dimensions and navigating successfully within it. We are distilling selected insect-inspired strategies to obtain novel solutions for navigation, hazard avoidance, altitude hold, stable flight, terrain following, and gentle deployment of payload. Such functionality provides potential solutions for future autonomous robotic space and planetary explorers. A BEES approach to developing lightweight low-power autonomous flight systems should be useful for flight control of such biomorphic flyers for both NASA and DoD needs. Recent biological studies of mammalian retinas confirm that representations of multiple features of the visual world are systematically parsed and processed in parallel. Features are mapped to a stack of cellular strata within the retina. Each of these representations can be efficiently modeled in semiconductor cellular nonlinear network (CNN) chips. We describe recent breakthroughs in exploring the feasibility of the unique blending of insect strategies of navigation with mammalian visual search, pattern recognition, and image understanding into hybrid biomorphic flyers for future planetary and terrestrial applications. We describe a few future mission scenarios for Mars exploration, uniquely enabled by these newly developed biomorphic flyers.

Space Flight↗
NASA NTRSDate not supplied

A Dual Linear/Circular Polarized Wideband Flat Panel Phased Array Antenna for K/Ka-band 6U CubeSat Communications Applications

Circular polarized (CP) electromagnetic waves are preferred for space-to-space and space-to-ground satellite communications (SATCOM). CubeSats with 6U sizes (1U represents a 10 cm x 10 cm x 10 cm), that will rotate together with the Moon as it orbits Earth require high gain CP antenna systems to maintain reliable communication links. Here, we have designed an 8x8 dual linear and dual circularly polarized phased array antenna (PAA) aperture that offers 22-28 GHz bandwidth, with maximum gain of 23 dBic, and beam scanning capability of ±50o with acceptable axial ratio over all scan angles. A stacked patch topology is selected to achieve wide impedance bandwidth. Each driven patch has two via feed point locations that are connected to grounded coplanar waveguide (CPW) feed structures. By utilizing phase shifters from the Anokiwave RFICs (AWMF-0165) employed for the beamforming network (BFN), we have generated both dual linear polarization and dual circular polarization in each patch. Each driven and parasitic patch is innovatively shaped to achieve excellent isolation between two feed points which, in turn, leads to low cross polarization, high efficiency and good axial ratio over the entire bandwidth. Each chip has eight outputs which feed one 2x2 sub-array consisting of four dual linear or dual circularly polarized driven patches, simultaneously. Each 2x2 sub-array of the 8x8 array are sequentially rotated which improves axial ratio performance when the antenna operates in the dual circularly polarized mode. By utilizing a mirror effect, cross-polarized fields are also improved when operated in a dual linear polarized mode. The 8x8 array aperture is simulated taking into account the effect of the multilayer printed circuit board (PCB) stack-up of the BFN and co-simulated with the power splitter outputs and chip outputs and results are compared with only passive array performance. The performance of the antenna is still excellent when non-ideal chip performances are included in the simulation analysis. The fabricated array will be tested for radiation patterns in the Antenna and Microwave Laboratory (AML) of the San Diego State University and the NASA Glenn Research Center (GRC) spherical near field chambers. The design of the 8x8 antenna array with BFN layout is shown in Fig. 1.

5G↗
NASA NTRS1984

Conceptual design of a hybrid Ge:Ga detector array

For potential applications in space infrared astronomy missions such as the Space Infrared Telescope Facility and the Large Deployable Reflector, integrated arrays of long-wavelength detectors are desired. The results of a feasibility study which developed a design for applying integrated array techniques to a long-wavelength (gallium-doped germanium) material to achieve spectral coverage between 30 and 200 microns are presented. An approach which builds up a two-dimensional array by stacking linear detector modules is presented. The spectral response of the Ge:Ga detectors is extended to 200 microns by application of uniaxial stress to the stack of modules. The detectors are assembled with 1 mm spacing between the elements. Multiplexed readout of each module is accomplished with integration sampling of a metal-oxide-semiconductor (MOS) switch chip. Aspects of the overall design, including the anticipated level of particle effects on the array in the space environment, a transparent electrode design for 200 microns response, estimates of optical crosstalk, and mechanical stress design calculations are included.

Parry, C. M.↗
NASA NTRS2006

Dual Common Planes for Time Multiplexing of Dual-Color QWIPs

A proposed improved method of externally controlled time multiplexing of the readouts of focal-plane arrays of pairs of stacked quantum-well infrared photodetectors (QWIPs) that operate in different wavelength bands is based on a dual-detector-common-plane circuit configuration. The method would be implemented in a QWIP integrated-circuit chip hybridized with a readout integrated-circuit (ROIC) chip.

Rafol, Sir B.↗
NASA NTRS1995

Multijunction InGaAs thermophotovoltaic power converter

The experimental performance of a multijunction monolithic In(0.53)Ga(0. 47)As power converter under blackbody irradiation is reported. Eight InGaAs PN junctions grown epitaxially on a semi-insulating wafer were monolithically integrated in series to boost the approximately 0.4 V photovoltage per typical InGaAs junction to over 3 volts for the 1 sq cm chip. This chip was originally designed and characterized for free-space 1.3 micron laser power beaming. This is the first report of such a multijunction TPV. This is not a traditional tandem cell in which the junctions are stacked vertically. The junctions are each about 1mm long by 1 cm wide and are laterally connected across the 1 sq cm device area. This multijunction design has the potential for lower I(sup 2)R power loss since the smaller PN junction area limits the current to one-eighth that of the equivalent surface area. In essence, the current is traded for voltage to avoid the I(sup 2)R loss, analogous to the way power utilities avoid I(sup 2)P loss in high-tension power lines, by transforming the high current, low voltage generated at a power plant into a high voltage at a low current before transmitting the power over great distances.

Wojtczuk, Steven↗
NASA NTRS1991

Laterally stacked Schottky diodes for infrared sensor applications

Laterally stacked Schottky diodes for infrared sensor applications are fabricated utilizing porous silicon having pores. A Schottky metal contract is formed in the pores, such as by electroplating. The sensors may be integrated with silicon circuits on the same chip with a high quantum efficiency, which is ideal for IR focal plane array applications due to uniformity and reproducibility.

Lin, True-Lon↗
NASA NTRS2004

A Two-Dimensional, Semiconducting Bolometer Array for HAWC

The Stratospheric Observatory For Infrared Astronomy's (SOFIA's) High resolution Airborne Wideband Camera (HAWC) will use an ion-implanted silicon bolometer array developed at NASA s Goddard Space Flight Center (GSFC). The GSFC Pop-Up Detectors (PUDs) use a unique folding technique to enable a 12 x 32 element closepacked array of bolometers with a filling factor greater than 95%. The HAWC detector uses a resistive metal film on silicon to provide frequency independent, approx. 50% absorption over the 40 - 300 micron band. The silicon bolometers are manufactured in 32-element rows within silicon frames using Micro Electro Mechanical Systems (MEMS) silicon etching techniques. The frames are then cut, "folded", and glued onto a metallized, ceramic, thermal bus "bar". Optical alignment using micrometer jigs ensures their uniformity and correct placement. The rows are then stacked side-by-side to create the final 12 x 32 element array. A kinematic Kevlar suspension system isolates the 200 mK bolometer cold stage from the rest of the 4K detector housing. GSFC - developed silicon bridge chips make electrical connection to the bolometers, while maintaining thermal isolation. The Junction Field Effect Transistor (JFET) preamplifiers for all the signal channels operate at 120 K, yet they are electrically connected and located in close proximity to the bolometers. The JFET module design provides sufficient thermal isolation and heat sinking for these, so that their heat is not detected by the bolometers. Preliminary engineering results from the flight detector dark test run are expected to be available in July 2004. This paper describes the array assembly and mechanical and thermal design of the HAWC detector and the JFET module.

Voellmer, George M.↗
NASA NTRS2001

Chip packaging technique

A hermetically sealed package for at least one semiconductor chip is provided which is formed of a substrate having electrical interconnects thereon to which the semiconductor chips are selectively bonded, and a lid which preferably functions as a heat sink, with a hermetic seal being formed around the chips between the substrate and the heat sink. The substrate is either formed of or includes a layer of a thermoplastic material having low moisture permeability which material is preferably a liquid crystal polymer (LCP) and is a multiaxially oriented LCP material for preferred embodiments. Where the lid is a heat sink, the heat sink is formed of a material having high thermal conductivity and preferably a coefficient of thermal expansion which substantially matches that of the chip. A hermetic bond is formed between the side of each chip opposite that connected to the substrate and the heat sink. The thermal bond between the substrate and the lid/heat sink may be a pinched seal or may be provided, for example by an LCP frame which is hermetically bonded or sealed on one side to the substrate and on the other side to the lid/heat sink. The chips may operate in the RF or microwave bands with suitable interconnects on the substrate and the chips may also include optical components with optical fibers being sealed into the substrate and aligned with corresponding optical components to transmit light in at least one direction. A plurality of packages may be physically and electrically connected together in a stack to form a 3D array.

Jayaraj, Kumaraswamy↗
NASA NTRS1977

Packaging of a large capacity magnetic bubble domain spacecraft recorder

A Solid State Spacecraft Data Recorder (SSDR), based on bubble domain technology, having a storage capacity of 10 to the 8th power bits, was designed and is being tested. The recorder consists of two memory modules each having 32 cells, each cell containing sixteen 100 kilobit serial bubble memory chips. The memory modules are interconnected to a Drive and Control Unit (DCU) module containing four microprocessors, 500 integrated circuits, a RAM core memory and two PROM's. The two memory modules and DCU are housed in individual machined aluminum frames, are stacked in brick fashion and through bolted to a base plate assembly which also houses the power supply.

Becker, F. J.↗