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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1977

Analysis of transmission error effects on the transfer of real-time simulation data

An analysis was made to determine the effect of transmission errors on the quality of data transferred from the Terminal Area Air Traffic Model to a remote site. Data formating schemes feasible within the operational constraints of the data link were proposed and their susceptibility to both random bit error and to noise burst were investigated. It was shown that satisfactory reliability is achieved by a scheme formating the simulation output into three data blocks which has the priority data triply redundant in the first block in addition to having a retransmission priority on that first block when it is received in error.

Credeur, L.↗
NASA NTRS1979

Development of non-volatile semiconductor memory

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Heikkila, W. W.↗
NASA NTRS1990

Adaptive box filters for removal of random noise from digital images

Adaptive box-filtering algorithms to remove random bit errors and to smooth noisy data have been developed. For both procedures, the standard deviation of those pixels within a local box surrounding each pixel is used. A series of two or three filters with decreasing box sizes can be run to clean up extremely noisy images and to remove bit errors near sharp edges. The second filter, for noise smoothing, is similar to the 'sigma filter' of Lee (1983). The technique effectively reduces speckle in radar images without eliminating fine details.

Eliason, Eric M.↗
NASA NTRS1999

Design of a 2.5 Gbps Optical Transmitter for the International Space Station

A high data rate laser transmitter assembly (LTA) has been designed as the source for an optical free-space communication link between the International Space Station and the 1-meter Optical Communication Telescope Laboratory (OCTL) to be built at the Table Mountain Facility (IMF, Wrightwood, CA). The transmitter design concept uses a fiber-based master oscillator power amplifier (MOPA) configuration with an average output power of 200 made at a 1550 nm transmit wavelength. This transmitter source is also designed to provide a signal at 980 nm to the Silicon-based focal plane array for the point-ahead beam control function. This novel integration of a 980 nm boresight signal allows the use of Silicon based imagers for the acquisition/tracking and point-ahead functions, yet permits the transmit signal to be at any wavelength outside the Silicon sensitivity. The LTA, a sub-system of the Flight Terminal, has been designed to have a selectable data rate from 155 - 2500 Mbps in discrete steps. It also incorporates a 2.5 Gbps pseudo-random bit sequence (PRBS) generator for complete link testing and diagnostics. The design emphasizes using commercial off the shelf components (COTS).

Ortiz, Gerardo G.↗
NASA NTRS2001

ATM QoS Experiments Using TCP Applications: Performance of TCP/IP Over ATM in a Variety of Errored Links

Asynchronous Transfer Mode (ATM) Quality of Service (QoS) experiments using the Transmission Control Protocol/Internet Protocol (TCP/IP) were performed for various link delays. The link delay was set to emulate a Wide Area Network (WAN) and a Satellite Link. The purpose of these experiments was to evaluate the ATM QoS requirements for applications that utilize advance TCP/IP protocols implemented with large windows and Selective ACKnowledgements (SACK). The effects of cell error, cell loss, and random bit errors on throughput were reported. The detailed test plan and test results are presented herein.

Frantz, Brian D.↗
NASA NTRS2003

Quantum Adiabatic Optimization and Combinatorial Landscapes

In this paper we analyze the performance of the Quantum Adiabatic Evolution (QAE) algorithm on a variant of Satisfiability problem for an ensemble of random graphs parametrized by the ratio of clauses to variables, gamma = M / N. We introduce a set of macroscopic parameters (landscapes) and put forward an ansatz of universality for random bit flips. We then formulate the problem of finding the smallest eigenvalue and the excitation gap as a statistical mechanics problem. We use the so-called annealing approximation with a refinement that a finite set of macroscopic variables (verses only energy) is used, and are able to show the existence of a dynamic threshold gamma = gammad, beyond which QAE should take an exponentially long time to find a solution. We compare the results for extended and simplified sets of landscapes and provide numerical evidence in support of our universality ansatz.

Smelyanskiy, V. N.↗
NASA NTRS2002

Mountain-Top-to-Mountain-Top Optical Link Demonstration

A mountain-top-to-mountain-top optical communications demonstration was conducted between the JPL Table Mountain Facility (TMF), Wrightwood, California, and Strawberry Peak (SP), Lake Arrowhead, California, during the months of August and September of 2000. The link was nearly horizontal at an altitude of 2 km and spanned a range of 46.8 km. A 780-nm multibeam beacon broadcast from TMF was received by the JPL Optical Communications Demonstrator (OCD) located at SP. The received beacon was utilized as a pointing reference to retransmit an 852-nm communications laser beam, modulated at 400 Mb/s by a PN7 pseudo-random bit stream (PRBS) sequence. The long atmospheric path resulted in atmospheric-turbulence-induced angle-of-arrival fluctuations of the beacon at the OCD aperture. A .ne-steering control loop was used to track the resulting beacon centroid motion and update the pointing of the communications laser beam transmitted from SP to TMF. Fried parameters, or r0, inferred from focal spot sizes received at SP were 4 to 5 cm whereas, using the spot sizes received at TMF, they were 2 to 3 cm. In both cases, theory predicts larger r0 values. The predicted angle-of-arrival fluctuations compare well with measured rms displacements exhibited by the focal spots at either end of the link. An uncompensated error of ~1.1 rad in the x-axis and ~2 rad in the y-axis was obtained using centroid data logged by the OCD. Average bit-error rates of 10-5 were recorded for extended periods of time. An atmospheric coherence length r0 of 3 to 5 cm was inferred using the focal-plane spot size measured on the CCD tracking sensor and compared to a predicted value of 5 to 7 cm using reasonable atmospheric models. The irradiance bounds required for the CCD tracking sensor to perform centroiding was found to range from 2000 to 3000 integrated pixel counts, although a more reliable range was 600 to 3000, indicating a dynamic range of 6 to 11 dB. The motion of the spot on the focal plane was also recorded and yielded rms angle-of-arrival-induced focal-plane displacement of 9 to 11 m, compared to a predicted value of 7.8 to 11 m. The irradiance measurements made with the OCD clearly indicate that best tracking performance is obtained when the mean received signal is 2000 to 2200 counts. The best tracking performance resulted in an rms uncompensated error of 1.1 rad. The uncompensated error appeared to increase with either an increase or decrease in mean beacon-signal level. The rms uncompensated error determined by deriving the beacon displacement power spectral density from the beacon centroid-versustime data and the rejection function of the control loop yielded a higher value of 3.4 rad.

Biswas, A.↗
DOE OSTI2025

Demystifying the Resilience of Large Language Models: An End-to-End Perspective

Deep neural networks are known to be resilient to random bit-wise faults in their parameters. However, this resilience has primarily been established through evaluations of classification models. The extent to which this claim holds for large-language models remains underexplored. In this work, we conduct an extensive measurement study on the impact of random bitwise faults in commercial-scale language models. We perform an in-depth analysis of the resulting generation outputs. We first expose that these language models are not truly resilient to random bit-flips. While aggregate metrics such as accuracy may suggest resilience, an in-depth inspection of the generated outputs shows significant degradation in text quality. Our analysis also shows that tasks requiring more complex reasoning suffer more from performance and quality degradation. Moreover, we extend our analysis to models with augmented reasoning capabilities, such as Chain-of-Thought or Mixture of Experts architectures, and characterize their failure scenarios under random bit-flips.

Sun, Yu↗
NASA NTRS1984

Fast decoding techniques for extended single-and-double-error-correcting Reed Solomon codes

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. For example, some 256K-bit dynamic random access memories are organized as 32K x 8 bit-bytes. Byte-oriented codes such as Reed Solomon (RS) codes provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special high speed decoding techniques for extended single and double error correcting RS codes. These techniques are designed to find the error locations and the error values directly from the syndrome without having to form the error locator polynomial and solve for its roots.

Costello, D. J., Jr.↗
NASA NTRS1979

Electrical Characterization of the RCA CDP1822SD Random Access Memory, Volume 1, Appendix a

Electrical characteristization tests were performed on 35 RCA CDP1822SD, 256-by-4-bit, CMOS, random access memories. The tests included three functional tests, AC and DC parametric tests, a series of schmoo plots, rise/fall time screening, and a data retention test. All tests were performed on an automated IC test system with temperatures controlled by a thermal airstream unit. All the functional tests, the data retention test, and the AC and DC parametric tests were performed at ambient temperatures of 25 C, -20 C, -55 C, 85 C, and 125 C. The schmoo plots were performed at ambient temperatures of 25 C, -55 C, and 125 C. The data retention test was performed at 25 C. Five devices failed one or more functional tests and four of these devices failed to meet the expected limits of a number of AC parametric tests. Some of the schmoo plots indicated a small degree of interaction between parameters.

Klute, A.↗
NASA NTRS1979

Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 1

Electrical characterization and qualification tests were performed on the RCA MWS5001D, 1024 by 1-bit, CMOS, random access memory. Characterization tests were performed on five devices. The tests included functional tests, AC parametric worst case pattern selection test, determination of worst-case transition for setup and hold times and a series of schmoo plots. The qualification tests were performed on 32 devices and included a 2000 hour burn in with electrical tests performed at 0 hours and after 168, 1000, and 2000 hours of burn in. The tests performed included functional tests and AC and DC parametric tests. All of the tests in the characterization phase, with the exception of the worst-case transition test, were performed at ambient temperatures of 25, -55 and 125 C. The worst-case transition test was performed at 25 C. The preburn in electrical tests were performed at 25, -55, and 125 C. All burn in endpoint tests were performed at 25, -40, -55, 85, and 125 C.

Klute, A.↗
DOE OSTI2025

A Cascaded Random Access Quantum Memory

Dynamic random access memory is critical to classical computing but notably absent in experimental quantum computers. Here we realize an 8-bit cascaded random access quantum memory using superconducting circuits and cavities and showcase the ability to perform arbitrary gate operations on it. In addition to individual error channels such as photon loss, quantum memories can also experience decoherence from many-body self-interaction. We characterize the origin and contributions of many-body infidelity throughout the memory cycle. We find that individual modes can be accessed with $\lesssim 1.5\%$ infidelity per mode and that the entire memory can be accessed in arbitrary order with an error rate below the depolarization threshold of the surface code, paving the way for fault-tolerant quantum memories.

Li, Ziqian [Stanford U., Appl. Phys. Dept.; Stanfo↗
NASA NTRS1978

A wide bandwidth CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. CCD shift register memories (8K bit) were used to construct a feasibility model 128 K-bit buffer memory system. Serial data that can have rates between 150 kHz and 4.0 MHz can be stored in 4K-bit, randomly-accessible memory blocks. Peak power dissipation during a data transfer is less than 7 W, while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. System expansion to accommodate parallel inputs or a greater number of memory blocks can be performed in a modular fashion. Since the control logic does not increase proportionally to increase in memory capacity, the power requirements per bit of storage can be reduced significantly in a larger system.

Siemens, K.↗
DOE OSTI2025

Traceable random numbers from a non-local quantum advantage

The unpredictability of random numbers is fundamental to both digital security and applications that fairly distribute resources. However, existing random number generators have limitations—the generation processes cannot be fully traced, audited and certified to be unpredictable. The algorithmic steps used in pseudorandom number generators are auditable, but they cannot guarantee that their outputs were a priori unpredictable given knowledge of the initial seed. Device-independent quantum random number generators can ensure that the source of randomness was unknown beforehand, but the steps used to extract the randomness are vulnerable to tampering. Here we demonstrate a fully traceable random number generation protocol based on device-independent techniques. Our protocol extracts randomness from unpredictable non-local quantum correlations, and uses distributed intertwined hash chains to cryptographically trace and verify the extraction process. This protocol forms the basis for a public traceable and certifiable quantum randomness beacon that we have launched. Over the first 40 days of operation, we completed the protocol 7,434 out of 7,454 attempts—a success rate of 99.7%. Each time the protocol succeeded, the beacon emitted a pulse of 512 bits of traceable randomness. The bits are certified to be uniform with error multiplied by actual success probability bounded by 2−64. Further, the generation of certifiable and traceable randomness represents a public service that operates with an entanglement-derived advantage over comparable classical approaches.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2010

Scaled CMOS Technology Reliability Users Guide

The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.

Microelectronics Reliability↗
NASA NTRS1990

32-Bit-Wide Memory Tolerates Failures

Electronic memory system of 32-bit words corrects bit errors caused by some common type of failures - even failure of entire 4-bit-wide random-access-memory (RAM) chip. Detects failure of two such chips, so user warned that ouput of memory may contain errors. Includes eight 4-bit-wide DRAM's configured so each bit of each DRAM assigned to different one of four parallel 8-bit words. Each DRAM contributes only 1 bit to each 8-bit word.

Buskirk, Glenn A.↗
NASA NTRS1977

Minimax decoding of cyclic block codes

A minimax decoding algorithm utilizing soft bit detection of an (n,k) cyclic block code is described which will permit the correction of up to n-k bit errors interspersed at random locations throughout the block. The decoding solution consists of: (1) identifying the ordered soft bit set and, (2) finding the minimum order solution to the resulting syndrome equations where the nonzero error vector components are constrained to be a subset of the soft bit set. An efficient implementation of the decoding operation is described. In essence, this algorithm focuses the correction capability of the code on those bit positions which have the lowest a posteriori probabilities of correct detection.

Greene, E. P.↗
NASA NTRS2004

Four-Channel PC/104 MIL-STD-1553 Circuit Board

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Cox, Gary L.↗