On optimal signals for phase-locked loops
Optimum signals for phase locked or delay locked loops determined as function of signal to noise ratio
Layland, J. W.↗
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Digital phase-locked loop
An digital phase-locked loop is provided for deriving a loop output signal from an accumulator output terminal. A phase detecting exclusive OR gate is fed by the loop digital input and output signals. The output of the phase detector is a bi-level digital signal having a duty cycle indicative of the relative phase of the input and output signals. The accumulator is incremented at a first rate in response to a first output level of the phase detector and at a second rate in response to a second output level of the phase detector.
Cliff, R. A.↗
Optimum design of hybrid phase locked loops
The design procedure of phase locked loops is described in which the analog loop filter is replaced by a digital computer. Specific design curves are given for the step and ramp input changes in phase. It is shown that the designed digital filter depends explicitly on the product of the sampling time and the noise bandwidth of the phase locked loop. This technique of optimization can be applied to the design of digital analog loops for other applications.
Lee, P.↗
Extrasensitive phase-locked-loop circuit
Modified phase-locked loop (PLL) generates clock from incoming data signal. To minimize effects of threshold phase-detector gain variations, the PLL uses a dither oscillator, a dither band-pass filter, and correlator instead of coherent amplitude detector.
Nyiri, E. J.↗
Cycle slipping in phase-locked loops.
First slip time of phase locked loop of arbitrary order shown as solution of first order linear differential equation
DIFFERENTIAL EQUATION↗
A note on phase-locked loops in space communications
Phase locked loops in space communications
DATA REDUCTION↗
Random walk techniques in the solution of first order digital phase-locked loops
First order digital phase locked loops analysis for single channel command system, using random walk techniques
Holmes, J. K.↗
Near optimum digital phase locked loops.
Near optimum digital phase locked loops are derived utilizing nonlinear estimation theory. Nonlinear approximations are employed to yield realizable loop structures. Baseband equivalent loop gains are derived which under high signal to noise ratio conditions may be calculated off-line. Additional simplifications are made which permit the application of the Kalman filter algorithms to determine the optimum loop filter. Performance is evaluated by a theoretical analysis and by simulation. Theoretical and simulated results are discussed and a comparison to analog results is made.
Polk, D. R.↗
Phase-lock-loop application for fiber optic receiver
Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.
Ruggles, Stephen L.↗
Digital communication and tracking - Limit-cycles in passive-filter phase-locked loops
Limit cycles in passive filter phase locked loops of digital communication and tracking systems
TRACKING FILTER↗
Phase-locked loops
The basic analysis and design procedures are described for the realization of analog phase-locked loops (APLL), hybrid phase-locked loops (HPLL), discrete phase-locked loops, and digital phase-locked loops (DPLL). Basic configurations are diagrammed, and performance curves are given. A discrete communications model is derived and developed. The use of the APLL as an optimum angle demodulator and the Kalman-Bucy approach to APLL design are discussed. The literature in the area of phase-locked loops is reviewed, and an extensive bibliography is given. Although the design of APLLs is fairly well documented, work on discrete, hybrid, and digital PLLs is scattered, and more will have to be done in the future to pinpoint the formal design of DPLLs.
Gupta, S. C.↗
Phase-locked loop FM demodulator
A conventional phase-locked loop is improved by replacing its phase detector with one comprising a linear ramp generator and a sample-and-hold circuit, thus eliminating the need for a lowpass loop filter, although the output of the sample-and-hold circuit may be filtered in the case of a very low level modulating signal on the incoming FM signal, but then filtering is not a difficult problem as in a conventional phase-locked loop. The result is FM demodulation by zero-order estimation. For FM demodulation by first-order estimation, the arithmetic difference between adjacent samples is formed, and using a second sample-and-hold circuit an arithmetic difference signal is produced as an input to a second ramp generator that is reset after each sampling cycle to generate a ramp the slope of which is a function of the arithmetic difference signal stored in the second sample-and-hold circuit. The ramp thus generated by the second ramp generator is arithmetically summed with the zero-estimation signal from the first sample-and-hold circuit to form a first-order estimation signal. Filtering such a first-order estimation signal is less of a problem than filtering a zero-order estimation signal.
Kirkham, Harold↗
Simplified formula for mean cycle-slip time of phase-locked loops with steady-state phase error.
Previous work shows that the mean time from lock to a slipped cycle of a phase-locked loop is given by a certain double integral. Accurate numerical evaluation of this formula for the second-order loop is extremely vexing because the difference between exponentially large quantities is involved. The presented article demonstrates a method in which a much-reduced precision program can be used to obtain the mean first-cycle slip time for a loop of arbitrary degree tracking at a specified SNR and steady-state phase error. It also presents a simple approximate formula that is asymptotically tight at higher loop SNR.
Tausworthe, R. C.↗
A phase lock loop system with a modulo 2n pi phase detector
Phase lock loop system with modulo 2n pi phase detector
MODULUS↗
Binary phase locked loops for Omega receivers
An all-digital phase lock loop (PLL) is considered because of a number of problems inherent in an employment of analog PLL. The digital PLL design presented solves these problems. A single loop measures all eight Omega time slots. Memory-aiding leads to the name of this design, the memory-aided phase lock loop (MAPLL). Basic operating principles are discussed and the superiority of MAPLL over the conventional digital phase lock loop with regard to the operational efficiency for Omega applications is demonstrated.
Chamberlin, K.↗
Threshold performance of phase locked loop demodulators.
Threshold performance of phase locked loop demodulators
Osborne, P.↗
An all digital phase locked loop for FM demodulation
Digital phase locked loop for FM signals demodulation, considering system nonlinear difference equation
Garodnick, J.↗
Response of an all digital phase-locked loop
An all digital phase-locked loop (DPLL) is designed, analyzed, and tested. Three specific configurations are considered, generating first, second, and third order DPLL's; and it is found, using a computer simulation of a noise spike, and verified experimentally, that of these configurations the second-order system is optimum from the standpoint of threshold extension. This substantiates results obtained for analog PLL's.
Garodnick, J.↗