Binary phase locked loops for Omega receivers

Abstract

An all-digital phase lock loop (PLL) is considered because of a number of problems inherent in an employment of analog PLL. The digital PLL design presented solves these problems. A single loop measures all eight Omega time slots. Memory-aiding leads to the name of this design, the memory-aided phase lock loop (MAPLL). Basic operating principles are discussed and the superiority of MAPLL over the conventional digital phase lock loop with regard to the operational efficiency for Omega applications is demonstrated.