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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Advanced Heterogeneous Integration Enabled by 3D Freestanding Membranes—From Material Growths to Applications

For the future of electronics such as bioelectronics, 3D integrated electronics, and bendable electronics, the need for flexibility and stackability of electronic products has substantially grown up. However, conventional wafer-based single-crystalline semiconductors cannot catch up with such trends because they are bound to thick rigid wafers such that they are neither flexible nor stackable. Although polymer-based organic electronic materials are more compatible as they are mechanically compliant and less costly than inorganic counterparts, their electronic/photonic performance is substantially inferior to that of single-crystalline inorganic materials. Such performance-mechanical compliance dilemma could be resolved by developing methods to obtain cheap, flexible, stackable, single-crystalline inorganic systems. Such dream electronic systems could be realized by producing single-crystalline freestanding membranes. For the past few decades, various layer transfer techniques (a.k.a layer liftoff techniques) have been developed to produce single-crystalline freestanding membranes. In today's talk, I will present the survey of the layer liftoff techniques and go over how these strategies unlock new ways of manufacturing advanced electronic systems. In addition, I will introduce unprecedented artificial heterostructure devices enabled by stacking of those freestanding 3D material membranes, e.g., the world's smallest vertically-stacked full-color micro-LEDs, the world's best multiferroic devices, chip-less wireless e-skin, and reconfigurable hetero-integrated chips with AI accelerators.

Kim, Jeehwan↗
DOE OSTI2022

Advanced Heterogeneous Integration Enabled by 3D Freestanding Membranes—From Material Growths to Applications

For the future of electronics such as bioelectronics, 3D integrated electronics, and bendable electronics, the need for flexibility and stackability of electronic products has substantially grown up. However, conventional wafer-based single-crystalline semiconductors cannot catch up with such trends because they are bound to thick rigid wafers such that they are neither flexible nor stackable. Although polymer-based organic electronic materials are more compatible as they are mechanically compliant and less costly than inorganic counterparts, their electronic/photonic performance is substantially inferior to that of single-crystalline inorganic materials. Such performance-mechanical compliance dilemma could be resolved by developing methods to obtain cheap, flexible, stackable, single-crystalline inorganic systems. Such dream electronic systems could be realized by producing single-crystalline freestanding membranes. For the past few decades, various layer transfer techniques (a.k.a layer liftoff techniques) have been developed to produce single-crystalline freestanding membranes. In today's talk, I will present the survey of the layer liftoff techniques and go over how these strategies unlock new ways of manufacturing advanced electronic systems. In addition, I will introduce unprecedented artificial heterostructure devices enabled by stacking of those freestanding 3D material membranes, e.g., the world's smallest vertically-stacked full-color micro-LEDs, the world's best multiferroic devices, chip-less wireless e-skin, and reconfigurable hetero-integrated chips with AI accelerators.

Kim, Jeehwan↗
DOE OSTI2024

Heterogeneous Integration Technologies for High-temperature, High-density, Low-profile Power Modules of Wide Bandgap Devices in Electric Drive Applications (Final Technical Report)

The goal of this project is to develop packaging technologies for making high-temperature, high-density, and low-profile wide-bandgap (WBG) power electronics modules for electric drives. These modules are aimed at enabling the DOE’s University Consortium to reach its 2025 inverter targets of ≥ 100 kW/L and ≤ 2.7 $/kW. The specific objectives are to: design and fabricate SiC half-bridge power modules with double-sided cooling and parasitic inductances < 5 nH, heat flux density > 400 W/cm 2 , and working junction temperature of 200 o C; design, fabricate, and deliver a gate driver with double-sided cooled modules for the construction of a 100 kW/L inverter at Oak Ridge National Lab; and design and prototype intelligent gate drivers with integrated current sensor and a low-profile DC-DC power supply with air-core transformer for testing power modules at 200 o C junction temperature. We followed an iterative technical approach of design, simulation, fabrication, and testing of various versions of modules, current sensors, and power supply. The state-of-the-art silicon carbide devices rated at 1.2 kV and 149 A were packaged by sintered-silver bonding on an aluminum nitride direct-bond-copper substrate for high thermal conductivity, high working temperature, and high joint reliability. Porous silver posts were used to interconnect the device’s source pads to the other direct-bond-copper substrate for low mechanical stresses, ease of manufacturing, and double-sided cooling. A current sensor based on package parasitic inductance was developed to measure switching current. A dynamic feedback scheme was developed to compensate the effect of parasitic resistance and temperature variation. A constant-current class-E dc-dc converter with air-core transformer was developed. Air-core transformer was used due to the unavailability of magnetic core at high temperatures. Gate driver and power supply were integrated with the double-side cooled, high temperature SiC power modules for testing the modules at 200 o C junction temperature. Double-pulse and continuous testing of the integrated technologies validated the design and fabrication of the three component technologies. Throughout the project, we overcame the challenge for design verification caused by low prototyping yield, which then helped train the graduate students, the future workforce, to learn the engineering know-how for low-cost manufacturing of reliable products. Below is a summary of the major accomplishments of this project: development of a prototyping process for fabricating double-side cooled (1200 V, 149 A) SiC phase-leg modules capable of working to 200 o C Tj; simulation and experimental verification of the improvement of thermo-mechanical reliability of the double-side cooled SiC phase-leg module by using rigid encapsulant; design and experimental validation of a current sensor based on package parasitic inductance and a compensation solution for eliminating the effect of parasitic resistance; design and experimental validation of a low-profile power supply with six-output air-core transformer for gate driver; functional demonstration of a SiC phase-leg module integrated with its gate driver, current sensor, and an air-core power supply at 200 o C Tj in a double-pulse switching test setup and Buck converter continuous test setup; successful completion of six PhD and two MS students who are or will work at Apple Inc., Tesla Inc., Wolfspeed Inc., Microchip Inc., Monolithic Power Systems Inc., and LG Magna Inc.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗