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All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

The Heterogeneous Integration of Electronic Components

Heterogeneous integration (HI) of electronics components is broadly recognized as a powerful and crucial enabler for the continued growth of computing and communication. From 2010 onwards, the value of HI is increasingly visible in the advanced packaging used in artificial intelligence, high-performance computing, smartphones and communications product implementations. In this Perspective, we argue that HI is crucial to semiconductors and more broadly to the continued evolution of computing and communications. We use leading-edge advanced packaging examples to represent the value, advancements and opportunities for HI. To succeed, it is critical to develop comprehensive HI roadmaps that inform collaborations across the design, manufacturing and reliability spectrum between systems architects, packaging and semiconductor technologists to common goals. Although this article does not provide a full roadmap, we instead detail additional parameters for artificial intelligence, smartphone and other cellular communication devices, and their constituent building blocks including interconnects, power electronics, photonics, thermal management, reliability, modelling and co-design, to foster greater collaboration opportunities among academia, research laboratories and industry.

42 ENGINEERING↗
DOE OSTI2022

2D materials-assisted heterogeneous integration of semiconductor membranes toward functional devices

Heterogeneous integration techniques allow the coupling of highly lattice-mismatched solid-state membranes, including semiconductors, oxides, and two-dimensional materials, to synergistically fuse the functionalities. The formation of heterostructures generally requires two processes: the combination of crystalline growth and a non-destructive lift-off/transfer process enables the formation of high-quality heterostructures. Although direct atomic interaction between the substrate and the target membrane ensures high-quality growth, the strong atomic bonds at the substrate/epitaxial film interface hinder the non-destructive separation of the target membrane from the substrate. Alternatively, a 2D material-coated compound semiconductor substrate can transfer the weakened (but still effective) surface potential field of the surface through the 2D material, allowing both high-quality epitaxial growth and non-destructive lift-off of the grown film. This Perspective reviews 2D/3D heterogeneous integration techniques, along with applications of III–V compound semiconductors and oxides. Here, the advanced heterogeneous integration methods offer an effective method to produce various freestanding membranes for stackable heterostructures with unique functionalities that can be applied to novel electrical, optoelectronic, neuromorphic, and bioelectronic systems.

2D materials↗
DOE OSTI2024

SIREN: Scaling Ion-Traps by REquiring iNnovative Heterogenous Integration

The SIREN (Scaling Ion Traps by Requiring iNnovative heterogenous integration) project explores the feasibility of heterogeneous integration (HI) as a transformative approach to scaling ion traps, a critical technology for advancing quantum computers and atomic clocks. Traditional ion trap architectures face significant challenges in scalability due to limitations in optical access, fabrication techniques, and material constraints. SIREN addresses these challenges by leveraging HI, which combines different materials and fabrication processes to create more complex and efficient ion trap structures. HI integrated structures can be manufactured without compromising the process to maintain compatibility to ion traps. This project focuses on integrating a separately fabricated waveguide with a fully functional ion trap. The respective alignment between the pieces needs to be accurate to less than 2 µm to ensure that the light from the waveguide can overlap with the trapping region. The fine alignment must also be maintained through an ultra-high vacuum bake, a critical step in preparing an ion trap experiment. The project's outcomes suggest that heterogeneous integration is a promising pathway for overcoming current scalability barriers, paving the way for the next generation of quantum technologies. SIREN's findings contribute significantly to the field, offering a scalable solution that could accelerate the development of practical quantum computers and highly accurate atomic clocks.

42 ENGINEERING↗
DOE OSTI2021

Study of an Integration Platform Based on an Adiabatic Active-Layer Waveguide Connection for InP Photonic Device Integration Mirroring That of Heterogeneous Integration on Silicon

In this work, a photonic device integration platform capable of integration of active-passive InP-based photonic devices without the use of material regrowth is introduced. The platform makes use of an adiabatic active-layer waveguide connection (ALWC) to move an optical beam between active and passive devices. The performance of this platform is analyzed using an example made up of four main sections: (1) a fiber coupling section for enabling vertical beam coupling from optical fiber into the photonic chip using a mode-matched surface grating with apodized duty cycles; (2) a transparent waveguide section for realizing passive photonic devices; (3) an adiabatic mode connection structure for moving the optical beam between passive and active device sections; and (4) an active device section for realizing active photonic devices. It is shown that the coupled surface grating, when added with a bottom gold reflector, can achieve a high chip-to-fiber coupling efficiency (CE) of 88.3% at 1550 nm. The adiabatic active-layer mode connection structure has an optical loss of lower than 1% (CE > 99%). The active device section can achieve an optical gain of 20 dB/mm with the use of only 3 quantum wells. The optimized structural parameters of the entire waveguide module are analyzed and discussed.

42 ENGINEERING↗
DOE OSTI2020

Widely tunable, heterogeneously integrated quantum-dot O-band lasers on silicon

Heterogeneously integrated lasers in the O-band are a key component in realizing low-power optical interconnects for data centers and high-performance computing. Quantum-dot-based materials have been particularly appealing for light generation due to their ultralow lasing thresholds, small linewidth enhancement factor, and low sensitivity to reflections. Here, we present widely tunable quantum-dot lasers heterogeneously integrated on silicon-on-insulator substrate. The tuning mechanism is based on Vernier dual-ring geometry, and a 47 nm tuning range with 52 dB side-mode suppression ratio is observed. These parameters show an increase to 52 nm and 58 dB, respectively, when an additional wavelength filter in the form of a Mach–Zehnder interferometer is added to the cavity. The Lorentzian linewidth of the lasers is measured as low as 5.3 kHz.

Malik, Aditya (ORCID:0000000334487577)↗
DOE OSTI2025

Ion Traps and Packaging for Heterogenous Integration - Chimera

Microfabricated surface ion traps and silicon-based photonics are critical technologies for scaling quantum systems. Current ion trap architectures face scalability and integration challenges due to limitations in optical access, fabrication techniques, and material compatibility. State-of-the-art quantum computers and atomic clocks are investigating monolithic integration, which necessitates custom traps for each ion species and has not overcome the integration hurdles presented by merging these technologies. The Chimera (Ion Traps and Packaging for Heterogeneous Integration) project proposes a novel approach utilizing heterogeneous integration (HI) of ion traps and photonic circuits. This separation of components allows for flexibility in ion trap design and reduces fabrication compromises. The Chimera project specifically designed an ion trap to interface vertically with a separately fabricated waveguide chip and demonstrates the first steps to integrating them at the packaging level. The ion trap features a large area of removed silicon, allowing the photonics chip outputs closer to the ion trap, improving alignment and packaging processes. The alignment must be accurate to < 1 µm to ensure that the light from the waveguide can overlap with the trapping region. This fine alignment must also be maintained through an ultra-high vacuum bake, a critical step in preparing an ion trap experiment. By combining separate chips, we demonstrate a new path for scaling trapped ion technology that is less reliant on monolithic integration. We successfully fabricated a trap with a large area of oxide removed, resulting in a region thinned to about 40 µm, a key milestone toward successful integration.

42 ENGINEERING↗
DOE OSTI2023

A universal metasurface transfer technique for heterogeneous integration

Metasurfaces offer a versatile platform for engineering the wavefront of light using nanostructures with subwavelength dimensions and hold great promise for dramatically miniaturizing conventional optical elements due to their small footprint and broad functionality. However, metasurfaces so far have been mainly demonstrated on bulky and planar substrates that are often orders of magnitude thicker than the metasurface itself. Conventional substrates not only nullify the reduced footprint advantage of metasurfaces, but also limit their application scenarios. The bulk substrate also determines the metasurface dielectric environment, with potentially undesired optical effects that undermine the optical performance. Here we develop a universal polymer-assisted transfer technique to tackle this challenge by decoupling the substrate employed on the fabrication of metasurfaces from that used for the target application. As an example, Huygens’ metasurfaces with 120 nm thickness in the visible range (532 nm) are demonstrated to be transferred onto a 100 nm thick freestanding SiN x membrane while maintaining excellent structural integrity and optical performance of diffraction-limited focusing. This transfer method not only enables the thinnest dielectric metalens to the best of our knowledge, but also opens up new opportunities in integrating cascaded and multilayer metasurfaces, as well as the heterogeneous integration with nonconventional substrates and various electronic/photonic devices.

42 ENGINEERING↗
NASA NTRS2001

Heterogeneous Integration, An Approach to High Density and High Flexibility Electronic Packaging

Key to the design of spacecraft for exploration of the outer planets will be the development of highly integrated and mass/volume efficient electronic systems. Exploration of the outer planets will require optimized propulsion approaches which mandates mass minimization. If one looks at a mission such as the Europa Lander, a high mass/volume efficiency feeds back directly into lower mass for radiation shielding. Concurrently the long mission lengths will drive the need for fault isolation and fault tolerance. The ability to build distributed electronic systems is an inherent requirement and one which is enabled by heterogeneous integration. The electronic packaging approach must be capable of interconnecting various components at a scale comparable with that on the components themselves (chip scale) and it must facilitate efficient integration of the electronics with elements of the spacecraft such as structure or antennae. The concept of 'Heterogeneous Integration' is being explored in the System On A Chip (SOAC) Project at JPL. The goal, of this approach to electronic packaging, is to enable the fabrication and assembly of complete electronic subsystems from components fabricated by a range of processes. Included in such a system could be MEMS sensors, SOI mixed signal ASICs, micro scale passive components and micro power. Secondarily the compact size will enable distributed architectures and integrated assemblies. Additional information is contained in the original extended abstract.

DAgostino, S. A.↗
NASA NTRS1995

Using an architectural approach to integrate heterogeneous, distributed software components

Many computer programs cannot be easily integrated because their components are distributed and heterogeneous, i.e., they are implemented in diverse programming languages, use different data representation formats, or their runtime environments are incompatible. In many cases, programs are integrated by modifying their components or interposing mechanisms that handle communication and conversion tasks. For example, remote procedure call (RPC) helps integrate heterogeneous, distributed programs. When configuring such programs, however, mechanisms like RPC must be used explicitly by software developers in order to integrate collections of diverse components. Each collection may require a unique integration solution. This paper describes improvements to the concepts of software packaging and some of our experiences in constructing complex software systems from a wide variety of components in different execution environments. Software packaging is a process that automatically determines how to integrate a diverse collection of computer programs based on the types of components involved and the capabilities of available translators and adapters in an environment. Software packaging provides a context that relates such mechanisms to software integration processes and reduces the cost of configuring applications whose components are distributed or implemented in different programming languages. Our software packaging tool subsumes traditional integration tools like UNIX make by providing a rule-based approach to software integration that is independent of execution environments.

Callahan, John R.↗
DOE OSTI2023

Heterogeneous Integration of Freestanding Bilayer Oxide Membrane for Multiferroicity

Transition metal oxides exhibit a plethora of electrical and magnetic properties described by their order parameters. In particular, ferroic orderings offer access to a rich spectrum of fundamental physics phenomena, in addition to a range of technological applications. The heterogeneous integration of ferroelectric and ferromagnetic materials is a fruitful way to design multiferroic oxides. The realization of freestanding heterogeneous membranes of multiferroic oxides is highly desirable. In this study, epitaxial BaTiO 3 /La 0.7 Sr 0.3 MnO 3 freestanding bilayer membranes are fabricated using pulsed laser epitaxy. The membrane displays ferroelectricity and ferromagnetism above room temperature accompanying the finite magnetoelectric coupling constant. Further, this study reveals that a freestanding heterostructure can be used to manipulate the structural and emergent properties of the membrane. In the absence of the strain caused by the substrate, the change in orbital occupancy of the magnetic layer leads to the reorientation of the magnetic easy-axis, that is, perpendicular magnetic anisotropy. These results of designing multiferroic oxide membranes open new avenues to integrate such flexible membranes for electronic applications.

36 MATERIALS SCIENCE↗
NASA NTRS2020

Design of Si micro-cone light concentrators for heterogeneous integration with MWIR FPAs

Using 3-D finite difference time domain (FDTD) modeling, it is shown that micro-cone arrays obtained by anisotropic wet etching of Si have high potential for concentrating light on compact photodetector mesas of mid-wave infrared (MWIR) focal plane arrays (FPAs). The proposed structures can be heterogeneously integrated with FPAs possessing high quantum efficiency. They can be used to reduce the thermal noise and, potentially, increase the operating temperature of FPAs while maintaining high sensitivity of the photodetectors.

Astratov, Vasily N.↗
DOE OSTI2021

32 Gbps heterogeneously integrated quantum dot waveguide avalanche photodiodes on silicon

We report a heterogeneous GaAs-based quantum dot (QD) avalanche photodiode (APD) on silicon with an ultralow dark current of 10 pA at − <#comment/> 1 V , 3 dB bandwidth of 20 GHz and record gain-bandwidth product (GBP) of 585 GHz. Furthermore, open eye diagrams up to 32 Gb/s are demonstrated at 1310 nm. The k-factor has been measured for these devices to be as low as 0.14. A polarization dependence on gain and bandwidth has been observed and investigated. This shows the potential to integrate a high-speed receiver in a wavelength division multiplexing (WDM) system on a QD-based silicon photonics platform.

Tossoun, Bassem↗
NASA NTRS2001

System Miniaturization Via Heterogeneous Integration of Electronic Devices for Deep Space Missions

The scientific devices designed for each of the Outer Planets Program Focuses will likely be groundbreaking not only with respect to their scientific role but also regarding the electronics required to perform such investigations. In the past, the performance of packaged electronics was limited by the components themselves, with minimal influence of the packaging technology. The rapid development of integrated circuit technology, however, has drastically increased the importance of packaging technology in the ultimate performance of devices. If not carefully considered in the overall design, the packaging may become the limiting factor in the operation of the system. Although industry is responsible for several significant accomplishments in the field of electronics packaging, deep space/outer planet missions must take into account additional requirements such as extremely low temperatures, high radiation levels, hermetic sealing, and severe size and weight limitations. Therefore, the present investigation has been designed to meet the needs of NASA's sensor intensive outer planets program by combining (using flip chip technology) an array of devices (including analog, digital, power volt-age, passives, and MEMS) into a miniaturized heterogeneous system and utilizing optical buses to enable autonomy. Additional information is contained in the original extended abstract.

DelCastillo, L.↗
DOE OSTI2026

Heterogeneous Integration of Flipped Oxide Heterostructure Membranes for Nanoelectronics

Freestanding complex oxide membranes enable the release and transfer of epitaxial films, offering new design freedoms for next‐generation electronics. While the LaAlO 3 /SrTiO 3 (LAO/STO) heterostructure exhibits remarkable tunable conductivity at its interface, the active interface remains buried beneath the substrate, limiting access to this functionality. Here, we demonstrate how the LAO/STO heterostructure, in membrane form, can be flipped and precisely positioned on silicon and other platforms using polymer‐free micromanipulation. The transferred membranes preserve atomically smooth surfaces, high crystallinity, and key electronic properties. Through the 44‐nm insulating STO layer, ultra‐low‐voltage electron‐beam lithography (ULV‐EBL) writes conductive nanostructures at the now‐accessible STO/LAO interface, offering the potential to function as programmable local gates that modulate charge carriers in the underlying silicon. The platform establishes a general strategy for integrating complex oxide heterostructures with semiconductors, quantum materials, and flexible substrates, enabling new architectures for reprogrammable nanoelectronic devices.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Heterogenous Integration of Boron-Doped p -Diamond with Monolayer n -MoS 2 for PN Junctions Operating at Room Temperature

Diamond has tremendous potential for power electronics, due to its superior thermal conductivity, large electric field strength, and high carrier mobilities. However, the absence of a reliable room temperature n-type transport has impeded any advancements in diamond-based electronics. Here, we circumvent this bottleneck by integrating n-type two-dimensional (2D) monolayers of molybdenum disulfide (MoS 2 ) with boron doped p-type single crystal diamond and demonstrate 2D/3D heterostructure-based PN junction diodes that operate at room temperature with excellent rectification characteristics. Our diodes achieve a maximum forward current density (J D ) of ∼4000 A/cm 2 , an ideality factor (η) value of ∼3.7, and a rectification ratio (RR) of 10 6 . We find that the origin of current rectification stems from the interlayer recombination of majority carriers driven by direct tunnelling (DT) and Fowler Nordheim (FN) tunnelling mechanisms. In conclusion, our demonstration can open new avenues for diamond-based power electronics through its integration with 2D materials.

2D/3D integration↗