Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “heavy ion testing”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1984

A guideline for heavy ion radiation testing for Single Event Upset (SEU)

A guideline for heavy ion radiation testing for single event upset was prepared to assist new experimenters in preparing and directing tests. How to estimate parts vulnerability and select an irradiation facility is described. A broad brush description of JPL equipment is given, certain necessary pre-test procedures are outlined and the roles and testing guidelines for on-site test personnel are indicated. Detailed descriptions of equipment needed to interface with JPL test crew and equipment are not provided, nor does it meet the more generalized and broader requirements of a MIL-STD document. A detailed equipment description is available upon request, and a MIL-STD document is in the early stages of preparation.

Nichols, D. K.↗
NASA NTRS2017

Failure Analysis of Heavy-Ion-Irradiated Schottky Diodes

In this paper, we use high- and low-magnification optical microscope images, thermal infrared camera images, and scanning electron microscope images to identify failure locations in heavy-ion-irradiated Schottky diodes. After failures have been identified, the parts were cross-sectioned to describe the structure of the failures and energy dispersive x-ray spectroscopy was used to characterize the materials in the failure structures.

Radiation effects↗
NASA NTRS1998

Programmable Logic Application Notes

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, heavy ion test results, and some total dose results.

Katz, Richard↗
NASA NTRS2017

Packaging Technology for Dielectric-Coating-Less Heavy Ion Radiation Testing of High-Voltage (HV) Electronic Parts

Testing high voltage (HV) electronic parts (greater than 300 V) for sudden event effects (SEE) caused by cosmic rays in the space environment, consisting of energetic heavy-ions, and neutron radiation in the upper atmosphere is a crucial step towards using these parts in spacecraft and aircraft. Due to the nature of cosmic radiation and neutrons, electronic parts are tested for SEE without any packaging and/or shielding over the top of the device. In the case of commercial HV parts, the top of the packaging is etched off and then a thin dielectric coating is placed over the part in order to avoid electrical arcing between the device surface and wire bonds and other components. Even though the effects of the thin dielectric layer on SEE testing can be accounted for, the dielectric layer significantly hinders post testing failure analysis. Replicating the test capability of state-of-the-art packaging while eliminating the need for post radiation test processing of the die surface (that obscures failure analysis) is the goal. To that end, a new packaging concept for HV parts has been developed that requires no dielectric coating over the part. Testing of prototype packages used with Schottky diodes (rated at 1200V) has shown no electrical arcing during testing and leakage currents during reverse bias testing are within the manufactures specifications.

High Voltage↗
NASA NTRS2006

Texas Instruments-Digital Signal Processor(TI-DSP)SMJ320F20 SEL Testing

This viewgraph presentation reviews the testing of the Texas Instrument Digital Signal Processor(TI-DSP)SMJ320F20. Tests were performed to screen for susceptibility to Single Event Latchup (SEL) and measure sensitivity as a function of Linear Energy Transfer (LET) for an application specific test setup. The Heavy Ion Testing of two TI-DSP SMJ320F240 devices experienced Single Event Latchup (SEL) conditions at an LET of 1.8 MeV/(mg/square cm) The devices were exposed from a fluence of 1.76 x l0(exp 3) to 5.00 x 10(exp 6) particles/square cm of the Neon, Argon and Krypton ion beams. For DI(sub DD) an average latchup current occurred at about 700mA, which is a magnitude of 10 over the nominal current of 700mA.

Sanders, Anthony B.↗
NASA NTRS1999

SRAM Based Re-programmable FPGA for Space Applications

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

Wang, J. J.↗
NASA NTRS1985

Trends in parts susceptibility to single event upset from heavy ions

New test data have been combined with published data to form a nearly comprehensive body of single event upset (SEU) test data for heavy ion irradiations. These data have been arranged to exibit the SEU susceptibility of devices by function, technology, and manufacturer. Clear trends emerge which should be useful in predicting future device performance.

Nichols, D. K.↗
NASA NTRS1986

Trends in parts susceptibility to single event upset from heavy ions

New test data from the Jet Propulsion Laboratory (JPL), The Aerospace Corporation, Rockwell International (ANAHEIM) and IRT have been combined with published data of JPL and Aerospace to form a nearly comprehensive body of single event upset (SEU) test data for heavy ion irradiations. This data has been arranged to exhibit the SEU susceptibility of devices by function, technology and manufacturer. Clear trends emerge which should be useful in predicting future device performance.

Nichols, D. K.↗
NASA NTRS2002

Single event upset susceptibility testing of the Xilinx Virtex II FPGA

Heavy ion testing of the Xilinx Virtex IZ was conducted on the configuration, block RAM and user flip flop cells to determine their single event upset susceptibility using LETs of 1.2 to 60 MeVcm^2/mg. A software program specifically designed to count errors in the FPGA is used to reveal L1/e values and single-event-functional interrupt failures.

FPGA Xilinx Virtex static test single event upset↗
NASA NTRS2002

Single event upset suspectibility testing of the Xilinx Virtex II FPGA

Heavy ion testing of the Xilinx Virtex II was conducted on the configuration, block RAM and user flip flop cells to determine their static single-event upset susceptibility using LETs of 1.2 to 60 MeVcm^2/mg. A software program specifically designed to count errors in the FPGA was used to reveal L1/e, values (the LET at which the cross section is l/e times the saturation cross-section) and single-event functional-interrupt failures.

FPGA Virtex II SEU↗
NASA NTRS2019

A TID and SEE Characterization of Multi-Terabit COTS 3D NAND Flash

Single-event effects and total ionizing dose testing are described for a 32-layer NAND flash memory, in both SLC and MLC configurations, with special considerations for unique three-dimensional test results. Extraction of three-dimensional heavy-ion test data presents a unique visualization of angular effects in NAND flash. Pattern dependence differences between SLC and MLC mode are noted, along with slightly non-uniform angular cross-section results due to the complex volume. Finally, TID data under different operating and bias conditions shows that the failure point remains the higher-voltage erasure circuitry.

Flash Memory↗
NASA NTRS2017

SEE Test Results for the Snapdragon 820

SEE test results are presented for proton, neutron, and heavy ion testing of the Qualcomm Snapdragon 820 and its support DDR4 device (in this case the SK Hynix 24 Gb LP DDR4 device H9HKNNNDGUMUBR-NMH). Processor crashes and DDR4 stuck bits are the primary SEE types for protons and neutrons. Test preparation difficulties and software limitations caused test efforts to be limited to processor crashes, SEFIs and SBU, and Stuck Bits in the DDR4 device. Interpretation of results is complicated by mixing of errors between devices.

Cui, Matthew↗