Effect of Annealing Conditions on Recovery of Lattice Damage in a High-Energy-Implanted 4H-SiC Superjunction PIN Diode
A high energy ion implantation system has been recently developed at the Tandem Van de Graaff facility at Brookhaven National Laboratory with tunable energy to 150 MeV capable of multi-step, deep implantation in 4H-SiC wafers with dopant atoms, such as B, P, Al, and N. Medium and high voltage devices with deep junctions can be fabricated using this system. Lattice strain introduced by the implantation process needs to be recovered and dopant atoms activated by appropriate annealing process as the device performance is strongly associated with the extent of recovery of the lattice. Using Synchrotron X-ray Rocking Curve Topography (SXRCT) and Reciprocal Space Mapping (RSM), the strain induced by high energy implantation of Al and N in 4H-SiC in different patterns are measured and mapped. It is observed that the strain levels correlate with the total fluence levels. PiN diodes fabricated on these implanted wafers were then annealed at temperatures ranging from 1700 °C to 2000 °C for 60 min. The SXRCT and RSM analysis of the annealed samples suggests that for the same annealing duration, higher temperature leads to better lattice recovery.