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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1985

New outlook on control of crystalline and chemical perfection during growth of silicon

Significant progress has been made in our understanding of the Czochralski crystal growth process with the realization that the incorporation of oxygen into silicon is directly related to the internal gettering capability of wafers during device fabrication. It was also recognized that the electronic properties exhibited by silicon during various stages of device fabrication were significantly affected by the thermal history of the silicon during the post-growth cool-down period. Turbulent melt convection, induced by unavoidable destabilizing thermal gradients, was found to interfere with homogeneous dopant (and oxygen) incorporation and to influence markedly the dynamics of nonequilibrium point defects in the solidified silicon matrix during the cool-down period. In view of the unavoidability of destabilizing thermal gradients in conventional crystal growth configurations, melt stabilization through the application of magnetic fields is generally considered a viable approach. Control of heat input to the melt through heat pipe systems, as used during growth of germanium, cannot be applied to industrial growth of silicon. Recent studies have shown that heat exchange systems located coaxially about a growing crystal can be used to stabilize and control not only heat transfer in the grown crystal, but also in the melt adjacent to the solidification interface.

Witt, A. F.↗
NASA NTRS2013

Nickel-Graphite Composite Compliant Interface and/or Hot Shoe Material

Next-generation high-temperature thermoelectric-power-generating devices will employ segmented architectures and will have to reliably withstand thermally induced mechanical stresses produced during component fabrication, device assembly, and operation. Thermoelectric materials have typically poor mechanical strength, exhibit brittle behavior, and possess a wide range of coefficient of thermal expansion (CTE) values. As a result, the direct bonding at elevated temperatures of these materials to each other to produce segmented leg components is difficult, and often results in localized microcracking at interfaces and mec hanical failure due to the stresses that arise from the CTE mismatch between the various materials. Even in the absence of full mechanical failure, degraded interfaces can lead to increased electrical and thermal resistances, which adversely impact conversion efficiency and power output. The proposed solution is the insertion of a mechanically compliant layer, with high electrical and thermal conductivity, between the low- and high-temperature segments to relieve thermomechanical stresses during device fabrication and operation. This composite material can be used as a stress-relieving layer between the thermoelectric segments and/or between a thermoelectric segment and a hot- or cold-side interconnect material. The material also can be used as a compliant hot shoe. Nickel-coated graphite powders were hot-pressed to form a nickel-graphite composite material. A freestanding thermoelectric segmented leg was fabricated by brazing the compliant pad layer between the high-temperature p- Zintl and low-temperature p-SKD TE segments using Cu-Ag braze foils. The segmented leg stack was heated in vacuum under a compressive load to achieve bonding. The novelty of the innovation is the use of composite material that re duces the thermomechanical stresses en - countered in the construction of high-efficiency, high-temperature therm - o-electric devices. The compliant pad enables the bonding of dissimilar thermoelectric materials while maintaining the desired electrical and thermal properties essential for efficient device operation. The modulus, CTE, electrical, and thermal conductances of the composite can be controlled by varying the ratio of nickel to graphite.

Firdosy, Samad A.↗
NASA NTRS2001

Silicon Carbide Electronic Devices

The status of emerging silicon carbide (SiC) widebandgap semiconductor electronics technology is briefly surveyed. SiC-based electronic devices and circuits are being developed for use in high-temperature, high-power, and/or high-radiation conditions under which conventional semiconductors cannot function. Projected performance benefits of SiC electronics are briefly illustrated for several applications. However, most of these operational benefits of SiC have yet to be realized in actual systems, primarily owing to the fact that the growth techniques of SiC crystals are relatively immature and device fabrication technologies are not yet sufficiently developed to the degree required for widespread, reliable commercial use. Key crystal growth and device fabrication issues that limit the performance and capability of high-temperature and/or high-power SiC electronics are identified. The electrical and material quality differences between emerging SiC and mature silicon electronics technology are highlighted.

Neudeck, P. G.↗
NASA NTRS1992

Progress in silicon carbide semiconductor technology

Silicon carbide semiconductor technology has been advancing rapidly over the last several years. Advances have been made in boule growth, thin film growth, and device fabrication. This paper wi11 review reasons for the renewed interest in SiC, and will review recent developments in both crystal growth and device fabrication.

Powell, J. A.↗
NASA NTRS1993

Nonlinear optical thin films

A focused approach to development and evaluation of organic polymer films for use in optoelectronics is presented. The issues and challenges that are addressed include: (1) material synthesis, purification, and the tailoring of the material properties; (2) deposition of uniform thin films by a variety of methods; (3) characterization of material physical properties (thermal, electrical, optical, and electro-optical); and (4) device fabrication and testing. Photonic materials, devices, and systems were identified as critical technology areas by the Department of Commerce and the Department of Defense. This approach offers strong integration of basic material issues through engineering applications by the development of materials that can be exploited as the active unit in a variety of polymeric thin film devices. Improved materials were developed with unprecedented purity and stability. The absorptive properties can be tailored and controlled to provide significant improvement in propagation losses and nonlinear performance. Furthermore, the materials were incorporated into polymers that are highly compatible with fabrication and patterning processes for integrated optical devices and circuits. By simultaneously addressing the issues of materials development and characterization, keeping device design and fabrication in mind, many obstacles were overcome for implementation of these polymeric materials and devices into systems. We intend to considerably improve the upper use temperature, poling stability, and compatibility with silicon based devices. The principal device application that was targeted is a linear electro-optic modulation etalon. Organic polymers need to be properly designed and coupled with existing integrated circuit technology to create new photonic devices for optical communication, image processing, other laser applications such as harmonic generation, and eventually optical computing. The progression from microscopic sample to a suitable film-forming material in a working device is a complex, multifaceted endeavor. It requires close attention to maintaining the optical properties of the electro-optic active portion of the polymer while manipulating the polymer structure to obtain the desired secondary polymer properties.

Leslie, Thomas M.↗
NASA NTRS1991

Silicon carbide, a semiconductor for space power electronics

After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the areas of crystal growth and device fabrication technology. High quality single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

Powell, J. Anthony↗
NASA NTRS1991

Silicon carbide, a semiconductor for space power electronics

After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the area of crystal growth and device fabrication technology. High quality of single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

Powell, J. A.↗
NASA NTRS1985

Amorphous silicon photovoltaic modules and test devices design, fabrication and testing

In July of 1984, Hughes and JPL initiated a contract for Hughes to design, fabricate and test 10 thin film Amorphous Silicon (a-Si) photovoltaic power modules. These modules were to be 1 ft x 4 ft in size. They were to be preceded by the delivery of 10 a-Si 4 in. square test devices. This effort is very timely since thin film PV development has progressed to the point where intermediate load power applications are on the horizon. It is important to know if current a-Si submodule design and manufacturing processes yield a product that is compatible with the packaging needed to meet a 20 to 30 year life span expectancy. The term submodule is assigned to an interconnected assembly of 28 a-Si cells deposited on a 1 foot square glass superstrate. These assemblies are equipped with electrical terminations, i.e., copper tabs at the four corners of the inverted submodules. It is these submodules that are to be interconnected and packaged into power modules, as opposed to the interconnected individual crystalline cells packaged into todays PV modules. A discussion of the fabrication methods and results follows.

Vanleeuwen, M.↗
NASA NTRS2006

Silicon Carbide Technology

Silicon carbide based semiconductor electronic devices and circuits are presently being developed for use in high-temperature, high-power, and high-radiation conditions under which conventional semiconductors cannot adequately perform. Silicon carbide's ability to function under such extreme conditions is expected to enable significant improvements to a far-ranging variety of applications and systems. These range from greatly improved high-voltage switching for energy savings in public electric power distribution and electric motor drives to more powerful microwave electronics for radar and communications to sensors and controls for cleaner-burning more fuel-efficient jet aircraft and automobile engines. In the particular area of power devices, theoretical appraisals have indicated that SiC power MOSFET's and diode rectifiers would operate over higher voltage and temperature ranges, have superior switching characteristics, and yet have die sizes nearly 20 times smaller than correspondingly rated silicon-based devices [8]. However, these tremendous theoretical advantages have yet to be widely realized in commercially available SiC devices, primarily owing to the fact that SiC's relatively immature crystal growth and device fabrication technologies are not yet sufficiently developed to the degree required for reliable incorporation into most electronic systems. This chapter briefly surveys the SiC semiconductor electronics technology. In particular, the differences (both good and bad) between SiC electronics technology and the well-known silicon VLSI technology are highlighted. Projected performance benefits of SiC electronics are highlighted for several large-scale applications. Key crystal growth and device-fabrication issues that presently limit the performance and capability of high-temperature and high-power SiC electronics are identified.

Neudeck, Philip G.↗
NASA NTRS1998

SiC Technology

Silicon carbide (SiC)-based semiconductor electronic devices and circuits are presently being developed for use in high-temperature, high-power, and/or high-radiation conditions under which conventional semiconductors cannot adequately perform. Silicon carbide's ability to function under such extreme conditions is expected to enable significant improvements to a far-ranging variety of applications and systems. These range from greatly improved high-voltage switching [1- 4] for energy savings in public electric power distribution and electric motor drives to more powerful microwave electronics for radar and communications [5-7] to sensors and controls for cleaner-burning more fuel-efficient jet aircraft and automobile engines. In the particular area of power devices, theoretical appraisals have indicated that SiC power MOSFET's and diode rectifiers would operate over higher voltage and temperature ranges, have superior switching characteristics, and yet have die sizes nearly 20 times smaller than correspondingly rated silicon-based devices [8]. However, these tremendous theoretical advantages have yet to be realized in experimental SiC devices, primarily due to the fact that SiC's relatively immature crystal growth and device fabrication technologies are not yet sufficiently developed to the degree required for reliable incorporation into most electronic systems [9]. This chapter briefly surveys the SiC semiconductor electronics technology. In particular, the differences (both good and bad) between SiC electronics technology and well-known silicon VLSI technology are highlighted. Projected performance benefits of SiC electronics are highlighted for several large-scale applications. Key crystal growth and device-fabrication issues that presently limit the performance and capability of high temperature and/or high power SiC electronics are identified.

Neudeck, Philip G.↗
NASA NTRS1993

Characterization of Si (sub X)Ge (sub 1-x)/Si Heterostructures for Device Applications Using Spectroscopic Ellipsometry

Spectroscopic ellipsometry (SE) characterization of several complex Si (sub X)Ge (sub 1-x)/Si heterostructures prepared for device fabrication, including structures for heterojunction bipolar transistors (HBT), p-type and n-type heterostructure modulation doped field effect transistors, has been performed. We have shown that SE can simultaneously determine all active layer thicknesses, Si (sub X)Ge (sub 1-x) compositions, and the oxide overlayer thickness, with only a general knowledge of the structure topology needed a priori. The characterization of HBT material included the SE analysis of a Si (sub X)Ge (sub 1-x) layer deeply buried (600 nanometers) under the silicon emitter and cap layers. In the SE analysis of n-type heterostructures, we examined for the first time a silicon layer under tensile strain. We found that an excellent fit can be obtained using optical constants of unstrained silicon to represent the strained silicon conduction layer. We also used SE to measure lateral sample homogeneity, providing quantitative identification of the inhomogeneous layer. Surface overlayers resulting from prior sample processing were also detected and measured quantitatively. These results should allow SE to be used extensively as a non-destructive means of characterizing Si (sub X)Ge (sub 1-x)/Si heterostructures prior to device fabrication and testing.

Sieg, R. M.↗
NASA NTRS2004

Web Growth Used to Confine Screw Dislocations to Predetermined Lateral Positions in 4H-SiC Epilayers

Silicon-carbide- (SiC-) based power devices could enable substantial aerospace electronics benefits over today's silicon-based electronics. However, present-day SiC wafers contain electrically harmful dislocations (including micropipes) that are unpredictably distributed in high densities across all commercial 4H- and 6H-SiC wafers. The NASA Glenn Research Center recently demonstrated a crystal growth process that moves SiC wafer dislocations to predetermined lateral positions in epitaxial layers so that they can be reproducibly avoided during subsequent SiC electronic device fabrication. The process starts by reactive ion etching mesa patterns with enclosed trench regions into commercial on-axis (0001) 4H- or 6H-SiC substrates. An example of a pregrowth mesa geometry with six enclosed triangular-shaped trench regions is shown. After the etch mask is stripped, homoepitaxial growth is carried out in pure stepflow conditions that enable thin cantilevers to grow laterally from the tops of mesas whose pregrowth top surfaces are not threaded by substrate screw dislocations. The image in the bottom figure shows the postgrowth structure that forms after the lateral cantilevers expand to coalesce and completely roof over each of the six triangular trench regions. Atomic force microscope (AFM) measurements of the roof revealed that three elementary screw dislocation growth spirals, each shown in the AFM insets of the bottom image on the previous page, formed in the film roof at three respective points of cantilever film coalescence. The image above shows the structure following an etch in molten potassium hydroxide (KOH) that produced surface etch pits at the dislocation defects. The larger KOH etch pits--S1, S2, and S3--shown in this image correspond to screw dislocations relocated to the final points of cantilever coalescence. The smaller KOH etch pits are consistent with epilayer threading edge dislocations from the pregrowth substrate mesa (P1, P3, and P4) and a final cantilever coalescence point (P2). No defects (i.e., no etch pits) are observed in other cantilevered portions of the film surface. On the basis of the principle of dislocation Burgers vector conservation, we hypothesize that all vertically propagating substrate dislocations in an enclosed trench region become combined into a single dislocation in the webbed film roof at the point of final roof coalescence. The point of final roof coalescence, and therefore the lateral location of a webbed roof dislocation, can be designed into the pregrowth mesa pattern. Screw dislocations with predetermined lateral positions can then be used to provide the new growth steps necessary for growing a 4H/6H-SiC epilayer with a lower dislocation density than the substrate. Devices fabricated on top of such films can be positioned to avoid the preplaced dislocations.

Powell, J. Anthony↗
NASA NTRS2009

Nanostructure devices and fabrication method

An ion flux is directed to a carbon nanotube to permanently shape, straighten and/or bend the carbon nanotube into a desired configuration. Such carbon nanotubes have many properties that make them ideal as probes for Scanning Probe Microscopy and many other applications.

Stevens, Ramsey M.↗
NASA NTRS2012

Quality Control Method for a Micro-Nano-Channel Microfabricated Device

A variety of silicon-fabricated devices is used in medical applications such as drug and cell delivery, and DNA and protein separation and analysis. When a fluidic device inlet is connected to a compressed gas reservoir, and the outlet is at a lower pressure, a gas flow occurs through the membrane toward the outside. The method relies on the measurement of the gas pressure over the elapsed time inside the upstream and downstream environments. By knowing the volume of the upstream reservoir, the gas flow rate through the membrane over the pressure drop can be calculated. This quality control method consists of measuring the gas flow through a device and comparing the results with a standard curve, which can be obtained by testing standard devices. Standard devices can be selected through a variety of techniques, both destructive and nondestructive, such as SEM, AFM, and standard particle filtration.

Grattoni, Alessandro↗
NASA NTRS2023

NASA Engineering and Safety Center Technical Bulletin No. 23-07: Best Practices for Fabrication of Microelectronic Devices

Material degradation during the fabrication of microelectronic devices has plagued the space industry for many years owing to the layering of many dissimilar metals to create these devices. Often, commonly used materials and systems are overlooked as potential sources of material degradation. This technical bulletin highlights extensive research to isolate probable causes of this degradation.

Best Practices↗
NASA NTRS2007

Tunable Antireflection Layers for Planar Bolometer Arrays

It remains a challenge to obtain high-efficiency coupling of far-infrared through millimeter radiation to large-format detector arrays. The conventional approach of increasing detector coupling is to use reflective backshorts. However, this approach often results in excessive systematic errors resulting from reflections off the backshort edge. An alternate approach to both increasing quantum efficiency and reducing systematics associated with stray light is to place an antireflective coating near the front surface of the array. When incorporated with a resistive layer and placed behind the detector focal plane, the AR coating can serve to prevent optical ghosting by capturing radiation transmitted through the detector. By etching a hexagonal pattern in silicon, in which the sizes of the hexes are smaller than the wavelength of incident radiation, it is possible to fabricate a material that has a controllable dielectric constant, thereby allowing for simple tunable optical device fabrication. To this end, we have fabricated and tested tunable silicon "honeycomb" AR layers and AR/resistive layer devices. These devices were fabricated entirely out of silicon in order to eliminate problems associated with differential contraction upon detector cooling.

Brown, Ari-David↗
NASA NTRS1986

Overcash, D. R.

The objectives of this investigation were to determine the characteristics of semiconductor devices at low temperatures. The output characteristics of several currently available semiconductor devices and devices fabricated at Marshall Space Flight Center were measured over a range of gate voltages. Large variations in low-temperature performance, not only from type to type, but from field effect transistor (FET) to FET of the same type were obtained. By increasing the carrier concentrations at low temperatures through extra heavy doping, metal oxide semiconductor field effect transistor (MOSFET) device was fabricated that operated at 4.2K. To verify the low-temperature operation of a heavily doped device, this procedure was repeated. Their noise spectrum was analyzed at 4.2K. Suggestions were made as to possible fabrication methods, techniques, and other semiconductor materials that might improve the device charactersitics at low temperatures. A procedure for using an electric field to drift dopants through the insulating oxide to produce a very thin, heavily doped region under the gate of a MOSFET was initiated. Capacitance s a function of voltage plots was suggested as a method for determining the level of dopant drift.

Source record↗
NASA NTRS1993

Development of Si(1-x)Ge(x) technology for microwave sensing applications

The progress for the first year of the work done under the Director's Discretionary Fund (DDF) research project entitled, 'Development of Si(1-x)Ge(x) Technology for Microwave Sensing Applications.' This project includes basic material characterization studies of silicon-germanium (SiGe), device processing on both silicon (Si) and SiGe substrates, and microwave characterization of transmission lines on silicon substrates. The material characterization studies consisted of ellipsometric and magneto-transport measurements and theoretical calculations of the SiGe band-structure. The device fabrication efforts consisted of establishing SiGe device processing capabilities in the Lewis cleanroom. The characterization of microwave transmission lines included studying the losses of various coplanar transmission lines and the development of transitions on silicon. Each part of the project is discussed individually and the findings for each part are presented. Future directions are also discussed.

Mena, Rafael A.↗