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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

A systolic architecture for the correlation and accumulation of digital sequences

A fully systolic architecture for the implementation of digital sequence correlator/accumulators is described. These devices consist of a two-dimensional array of processing elements that are conceived for efficient fabrication in Very Large Scale Integrated (VLSI) circuits. A custom VLSI chip that was implemented using these concepts is described. The chip, which contains a four-lag three-level sequence correlator and four bits of accumulation with overflow detection, was designed using the Integrated UNIX-Based Computer Aided Design (CAD) System. Applications of such devices include the synchronization of coded telemetry data, alignment of both real time and non-real time Very Large Baseline Interferometry (VLBI) signals, and the implementation of digital filters and processes of many types.

Deutsch, L. J.↗
NASA NTRS1986

A computer graphics pilot project - Spacecraft mission support with an interactive graphics workstation

The NASA Computer Graphics Pilot Project was undertaken to enhance the quality control, productivity and efficiency of mission support operations at the Goddard Operations Support Computing Facility. The Project evolved into a set of demonstration programs for graphics intensive simulated control room operations, particularly in connection with the complex space missions that began in the 1980s. Complex mission mean more data. Graphic displays are a means to reduce the probabilities of operator errors. Workstations were selected with 1024 x 768 pixel color displays controlled by a custom VLSI chip coupled to an MC68010 chip running UNIX within a shell that permits operations through the medium of mouse-accessed pulldown window menus. The distributed workstations run off a host NAS 8040 computer. Applications of the system for tracking spacecraft orbits and monitoring Shuttle payload handling illustrate the system capabilities, noting the built-in capabilities of shifting the point of view and rotating and zooming in on three-dimensional views of spacecraft.

Hagedorn, John↗
NASA NTRS1987

System architecture of a gallium arsenide one-gigahertz digital IC tester

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

Fouts, Douglas J.↗
NASA NTRS1987

Real-time data compressor for Eos-class missions

A conceptual design for a real-time VLSI compressor capable of processing rate up to one gigabit per second is presented. This scheme is capable of providing a three-to-one distortion-free data reduction factor to both the High Resolution Imaging Spectrometer and processed SAR imaging data. The design uses a VLSI parallel/piplined architecture capable of processing at a real time rate. The design consists of a parallel array of VLSI compressor modules. Each module is built on a single customized VLSI chip using existing state-of-the-art semiconductor technology.

Lee, Jun-Ji↗
NASA NTRS1987

Sensing and perception research for space telerobotics at JPL

PIFLEX is a pipelined-image processor that can perform elaborate computations whose exact nature is not fixed in the hardware, and that can handle multiple images. A wire-wrapped prototype PIFEX module has been produced and debugged, using a version of the convolver composed of three custom VLSI chips (plus the line buffers). A printed circuit layout is being designed for use with a single-chip convolver, leading to production of a PIFEX with about 120 modules. A high-level language for programming PIFEX has been designed, and a compiler will be written for it. The camera calibration software has been completed and tested. Two more terms in the camera model, for lens distortion, probably will be added later. The acquisition and tracking system has been designed and most of it has been coded in Pascal for the MicroVAX-II. The feature tracker, motion stereo module and stereo matcher have executed successfully. The model matcher is still under development, and coding has begun on the tracking initializer. The object tracker was running on a different computer from the VAX, and preliminary runs on real images have been performed there. Once all modules are working, optimization and integration will begin. Finally, when a sufficiently large PIFEX is available, appropriate parts of acquisition and tracking, including much of the feature tracker, will be programmed into PIFEX, thus increasing the speed and robustness of the system.

Gennery, Donald B.↗
NASA NTRS1990

A VLSI implementation for synthetic aperture radar image processing

A simple physical model for the Synthetic Aperture Radar (SAR) is presented. This model explains the one dimensional and two dimensional nature of the received SAR signal in the range and azimuth directions. A time domain correlator, its algorithm, and features are explained. The correlator is ideally suited for VLSI implementation. A real time SAR architecture using these correlators is proposed. In the proposed architecture, the received SAR data is processed using one dimensional correlators for determining the range while two dimensional correlators are used to determine the azimuth of a target. The architecture uses only three different types of custom VLSI chips and a small amount of memory.

Premkumar, A.↗
NASA NTRS1992

The VLBA correlator: Real-time in the distributed era

The correlator is the signal processing engine of the Very Long Baseline Array (VLBA). Radio signals are recorded on special wideband (128 Mb/s) digital recorders at the 10 telescopes, with sampling times controlled by hydrogen maser clocks. The magnetic tapes are shipped to the Array Operations Center in Socorro, New Mexico, where they are played back simultaneously into the correlator. Real-time software and firmware controls the playback drives to achieve synchronization, compute models of the wavefront delay, control the numerous modules of the correlator, and record FITS files of the fringe visibilities at the back-end of the correlator. In addition to the more than 3000 custom VLSI chips which handle the massive data flow of the signal processing, the correlator contains a total of more than 100 programmable computers, 8-, 16- and 32-bit CPUs. Code is downloaded into front-end CPU's dependent on operating mode. Low-level code is assembly language, high-level code is C running under a RT OS. We use VxWorks on Motorola MVME147 CPU's. Code development is on a complex of SPARC workstations connected to the RT CPU's by Ethernet. The overall management of the correlation process is dependent on a database management system. We use Ingres running on a Sparcstation-2. We transfer logging information from the database of the VLBA Monitor and Control System to our database using Ingres/NET. Job scripts are computed and are transferred to the real-time computers using NFS, and correlation job execution logs and status flow back by the route. Operator status and control displays use windows on workstations, interfaced to the real-time processes by network protocols. The extensive network protocol support provided by VxWorks is invaluable. The VLBA Correlator's dependence on network protocols is an example of the radical transformation of the real-time world over the past five years. Real-time is becoming more like conventional computing. Paradoxically, 'conventional' computing is also adopting practices from the real-time world: semaphores, shared memory, light-weight threads, and concurrency. This appears to be a convergence of thinking.

Wells, D. C.↗
NASA NTRS1994

From neural-based object recognition toward microelectronic eyes

Engineering neural network systems are best known for their abilities to adapt to the changing characteristics of the surrounding environment by adjusting system parameter values during the learning process. Rapid advances in analog current-mode design techniques have made possible the implementation of major neural network functions in custom VLSI chips. An electrically programmable analog synapse cell with large dynamic range can be realized in a compact silicon area. New designs of the synapse cells, neurons, and analog processor are presented. A synapse cell based on Gilbert multiplier structure can perform the linear multiplication for back-propagation networks. A double differential-pair synapse cell can perform the Gaussian function for radial-basis network. The synapse cells can be biased in the strong inversion region for high-speed operation or biased in the subthreshold region for low-power operation. The voltage gain of the sigmoid-function neurons is externally adjustable which greatly facilitates the search of optimal solutions in certain networks. Various building blocks can be intelligently connected to form useful industrial applications. Efficient data communication is a key system-level design issue for large-scale networks. We also present analog neural processors based on perceptron architecture and Hopfield network for communication applications. Biologically inspired neural networks have played an important role towards the creation of powerful intelligent machines. Accuracy, limitations, and prospects of analog current-mode design of the biologically inspired vision processing chips and cellular neural network chips are key design issues.

Sheu, Bing J.↗
NASA NTRS1989

VLSI processors for signal detection in SETI

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

NASA Program Exobiology↗
NASA NTRS2006

The Zero-Degree Detector System

We will report on a detector system used for accelerator measurement of nuclear fragmentation cross sections. This system consists of two detector planes, each carrying a ring of 8 detectors. Each detector has 64 pads. These two detector planes are arranged facing each other so that the matching detector pads on each plane form a two element charged particle telescope. Each of these telescopes is capable of determining the elemental identity of nuclear fragments passing through it. The system is used to measure light fragment production in the presence of heavier fragments. We will present a detailed discussion of the 64-pad detector design, the substrate design. The front-end electronics used to read out the signals is based on a custom VLSI chip developed for the Advanced Thin Ionization Calorimeter experiment which has been flown successfully twice in Antarctica. Each of these chips has 16 channels and each channel consists of a charge-sensitive preamplifier followed by a shaping amplifier and a track-and-hold circuit. The track-and-hold circuits are connected via a multiplexer to an output line driver. This allows the held signals to be presented, one-by-one via a common data line to a analog-to-digital converter. Because the output line driver can be placed in a high input impedance state when not in use, it is possible to daisy-change many chips on the same common data line. The front-end electronics and data readout scheme will be discussed in detail. The Zero Degree Detector has been used in several accelerator experiments conducted at the NASA Space Radiation Laboratory and the Alternating Gradient Synchrotron at Brookhaven National Laboratory as well as at the HIMAC accelerator in Japan. We will show examples of data taken at these accelerator runs to demonstrate how the system works.

Adams, James H.↗
NASA NTRS1985

A laser plotting system for VLSI chip layouts

One of the most time consuming facets of custom Very Large Scale Integration (VLSI) design is obtaining hardcopy plots of the mask geometries of cells and chips. The traditional method of generating these plots is to use a multicolor pen plotter. Pen plotters are inherently slow and the plotting speed increases linearly with the number of edges that must be plotted. A moderate custom chip design at the Jet Propulsion Laboratory (JPL) now consists of more than 200,000 such edges and can take as much as eight hours to plot using a pen plotter. Software is described that was written at JPL to produce similar plots using a laser printer. It is shown that, for rather small layouts, the laser printer can provide nearly instantaneous turnaround. For moderate to large chip designs, the laser printer provides a factor of five or more improvement is speed over pen plotting.

Deutsch, L. J.↗
NASA NTRS1993

Microelectronic Chips For Radiation-Dose Tests

Custom-made single-chip complementary metal-oxide semiconductor (CMOS) integrated circuit designed to reveal effects of ionizing radiation on itself and similar integrated circuits. Potential terrestrial use: safety-oriented monitoring of ionizing radiation at nuclear powerplants, nuclear-waste sites, and the like.

Buehler, Martin G.↗
DOE OSTI2020

China’s Bid To Lead Artificial Intelligence Chip Development within the Decade

In 2017, the Chinese government announced an ambitious, broad strategy to become the global leader in artificial intelligence (AI) theories, technologies, and applications by 2030 and indicated that China’s ability to indigenously produce cutting-edge AI chips would be integral to its success. China’s goal to become a dominant producer of AI hardware within a decade is a bold undertaking because China faces domestic chip production challenges and fierce competition from US chip producers. Our review of Chinese AI chip product lines shows various levels where Chinese companies compete with global firms in the production chain. China lacks a robust indigenous AI chip production infrastructure, and the United States and its allies are tightening controls on the supply of advanced semiconductor manufacturing equipment (SME) and electronic design automation (EDA) software to China. In contrast to their Chinese counterparts, US companies operate in all areas of AI chip production and have consistently driven the development of new chip designs. AI chip production is a costly endeavor, and China’s chip producers currently lack the customer base to lead global AI chip development by the 2030 goal. An expanded customer base may help China attract the necessary expertise to bolster its AI chip production chain. This would also help Chinese producers make their investments in the requisite technology economically sustainable. Chinese researchers continue to pursue promising next-generation AI chip designs, such as neuromorphic computing-based architectures, which in the next five to ten years could position Chinese companies to make or contribute to key innovations in the field.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2024

Mixed domain coherent link with electrically reconfigurable IMDD and coherent modes for O-band data center applications

We report the first O-band link with electrically reconfigurable intensity-modulation direct-detection (IMDD) and coherent operation using custom silicon photonic chips packaged with commercial electronic chips. Transmission below the KP4-FEC threshold is shown using commercial 53 Gbaud PAM4 digital signal processing (DSP) for 16QAM (200 Gbps/ λ ) and PAM4 (100 Gbps/ λ ). Efficient operation of the packaged full link at 12 and 11.2 pJ/bit is achieved for the PAM4 and 16QAM modes, respectively.

Misak, Stephen (ORCID:0000000154973084)↗
NASA NTRS1981

SAR processing on the MPP

The processing of synthetic aperture radar (SAR) signals using the massively parallel processor (MPP) is discussed. The fast Fourier transform convolution procedures employed in the algorithms are described. The MPP architecture comprises an array unit (ARU) which processes arrays of data; an array control unit which controls the operation of the ARU and performs scalar arithmetic; a program and data management unit which controls the flow of data; and a unique staging memory (SM) which buffers and permutes data. The ARU contains a 128 by 128 array of bit-serial processing elements (PE). Two-by-four surarrays of PE's are packaged in a custom VLSI HCMOS chip. The staging memory is a large multidimensional-access memory which buffers and permutes data flowing with the system. Efficient SAR processing is achieved via ARU communication paths and SM data manipulation. Real time processing capability can be realized via a multiple ARU, multiple SM configuration.

Batcher, K. E.↗
NASA NTRS2003

Characterization of Pixelated Cadmium-Zinc-Telluride Detectors for Astrophysical Applications

Comparisons of charge sharing and charge loss measurements between two pixelated Cadmium-Zinc-Telluride (CdZnTe) detectors are discussed. These properties along with the detector geometry help to define the limiting energy resolution and spatial resolution of the detector in question. The first detector consists of a 1-mm-thick piece of CdZnTe sputtered with a 4x4 array of pixels with pixel pitch of 750 microns (inter-pixel gap is 100 microns). Signal readout is via discrete ultra-low-noise preamplifiers, one for each of the 16 pixels. The second detector consists of a 2-mm-thick piece of CdZnTe sputtered with a 16x16 array of pixels with a pixel pitch of 300 microns (inter-pixel gap is 50 microns). This crystal is bonded to a custom-built readout chip (ASIC) providing all front-end electronics to each of the 256 independent pixels. These detectors act as precursors to that which will be used at the focal plane of the High Energy Replicated Optics (HERO) telescope currently being developed at Marshall Space Flight Center. With a telescope focal length of 6 meters, the detector needs to have a spatial resolution of around 200 microns in order to take full advantage of the HERO angular resolution. We discuss to what degree charge sharing will degrade energy resolution but will improve our spatial resolution through position interpolation.

Gaskin, Jessica↗
NASA NTRS2012

Demonstration of the Wide-Field Imaging Interferometer Testbed Using a Calibrated Hyperspectral Image Projector

The Wide-field Imaging Interferometer testbed (WIIT) at NASA's Goddard Space Flight Center uses a dual-Michelson interferometric technique. The WIIT combines stellar interferometry with Fourier-transform interferometry to produce high-resolution spatial-spectral data over a large field-of-view. This combined technique could be employed on future NASA missions such as the Space Infrared Interferometric Telescope (SPIRIT) and the Sub-millimeter Probe of the Evolution of Cosmic Structure (SPECS). While both SPIRIT and SPECS would operate at far-infrared wavelengths, the WIIT demonstrates the dual-interferometry technique at visible wavelengths. The WIIT will produce hyperspectral image data, so a true hyperspectral object is necessary. A calibrated hyperspectral image projector (CHIP) has been constructed to provide such an object. The CHIP uses Digital Light Processing (DLP) technology to produce customized, spectrally-diverse scenes. CHIP scenes will have approximately 1.6-micron spatial resolution and the capability of . producing arbitrary spectra in the band between 380 nm and 1.6 microns, with approximately 5-nm spectral resolution. Each pixel in the scene can take on a unique spectrum. Spectral calibration is achieved with an onboard fiber-coupled spectrometer. In this paper we describe the operation of the CHIP. Results from the WIIT observations of CHIP scenes will also be presented.

Bolcar, Matthew R.↗
DOE OSTI2021

System-on-Chip approach microwave diagnostics development for burning plasma

System-on-chip (SoC) millimeter wave integrated circuit technology has been developed and employed in chip heterodyne radiometers in Electron Cyclotron Emission Imaging (ECEI) and Microwave Imaging Reflectometer (MIR) on the DIII-D tokamak for 2D electron temperature and density fluctuation diagnostics. The W-band (75-110 GHz) ECEI system has been employed with 20 poloidal horn receiver modules with customized monolithic integrated circuit chips and internal local oscillator coupling path. The new SoC approach demonstrates > 30 dB additional gain on the receiver and 95% electronics noise suppression compared to the previous Schottky diode mixer array . An F-band (110-140 GHz) receiver chip has been developed to measure MHD and turbulence behavior on the DIII-D high-field side, such as Alfven eigenmodes. Furthermore, it can image pedestal structure evolution on fusion facilities with stronger magnetic fields, such as ASDEX-U, EAST, HL-2M, and LHD. The F-band chip performance has been tested in the laboratory. Also, V-band (55-75 GHz) transmitter and receiver modules (55-75 GHz) have been developed for DIII-D and NSTX-U Furthermore, microwave Imaging Reflectometer (MIR) application suitability for 2D density fluctuation imaging on the pedestal region.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗