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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2006

Control of Technology Transfer at JPL

Controlled Technology: 1) Design: preliminary or critical design data, schematics, technical flow charts, SNV code/diagnostics, logic flow diagrams, wirelist, ICDs, detailed specifications or requirements. 2) Development: constraints, computations, configurations, technical analyses, acceptance criteria, anomaly resolution, detailed test plans, detailed technical proposals. 3) Production: process or how-to: assemble, operated, repair, maintain, modify. 4) Manufacturing: technical instructions, specific parts, specific materials, specific qualities, specific processes, specific flow. 5) Operations: how-to operate, contingency or standard operating plans, Ops handbooks. 6) Repair: repair instructions, troubleshooting schemes, detailed schematics. 7) Test: specific procedures, data, analysis, detailed test plan and retest plans, detailed anomaly resolutions, detailed failure causes and corrective actions, troubleshooting, trended test data, flight readiness data. 8) Maintenance: maintenance schedules and plans, methods for regular upkeep, overhaul instructions. 9) Modification: modification instructions, upgrades kit parts, including software

Jet Propulsion Laboratory (JPL)↗
NASA NTRS1989

Evaluating local indirect addressing in SIMD proc essors

In the design of parallel computers, there exists a tradeoff between the number and power of individual processors. The single instruction stream, multiple data stream (SIMD) model of parallel computers lies at one extreme of the resulting spectrum. The available hardware resources are devoted to creating the largest possible number of processors, and consequently each individual processor must use the fewest possible resources. Disagreement exists as to whether SIMD processors should be able to generate addresses individually into their local data memory, or all processors should access the same address. The tradeoff is examined between the increased capability and the reduced number of processors that occurs in this single instruction stream, multiple, locally addressed, data (SIMLAD) model. Factors are assembled that affect this design choice, and the SIMLAD model is compared with the bare SIMD and the MIMD models.

Middleton, David↗
NASA NTRS1974

STRCMACS: An extensive set of Macros for structured programming in OS/360 assembly language

Two techniques are discussed that have been most often referred to as structured programming. One is that of programming with high level control structures (such as the if and while) replacing the branch instruction (goto-less programming); the other is the process of developing a program by progressively refining descriptions of components in terms of more primitive components (called stepwise refinement or top-down programming). In addition to discussing what these techniques are, it is shown why their use is advised and how both can be implemented in OS assembly language by the use of a special macro instruction package.

Barth, C. W.↗
NASA NTRS1979

Interpretive computer simulator for the NASA Standard Spacecraft Computer-2 (NSSC-2)

An Interpretive Computer Simulator (ICS) for the NASA Standard Spacecraft Computer-II (NSSC-II) was developed as a code verification and testing tool for the Annular Suspension and Pointing System (ASPS) project. The simulator is written in the higher level language PASCAL and implented on the CDC CYBER series computer system. It is supported by a metal assembler, a linkage loader for the NSSC-II, and a utility library to meet the application requirements. The architectural design of the NSSC-II is that of an IBM System/360 (S/360) and supports all but four instructions of the S/360 standard instruction set. The structural design of the ICS is described with emphasis on the design differences between it and the NSSC-II hardware. The program flow is diagrammed, with the function of each procedure being defined; the instruction implementation is discussed in broad terms; and the instruction timings used in the ICS are listed. An example of the steps required to process an assembly level language program on the ICS is included. The example illustrates the control cards necessary to assemble, load, and execute assembly language code; the sample program to to be executed; the executable load module produced by the loader; and the resulting output produced by the ICS.

Smith, R. S.↗
NASA NTRS1974

Recommended practices for encapsulating high voltage assemblies

Preparation and encapsulation of high voltage assemblies are considered. Related problems in encapsulating are brought out in these instructions. A test sampling of four frequently used encapsulating compounds is shown in table form. The purpose of this table is to give a general idea of the working time available and the size of the container required for mixing and de-aerating.

Tankisley, E. W.↗
NASA NTRS2008

Developing Humanoid Robots for Real-World Environments

Humanoids are steadily improving in appearance and functionality demonstrated in controlled environments. To address the challenges of operation in the real-world, researchers have proposed the use of brain-inspired architectures for robot control, and the use of robot learning techniques that enable the robot to acquire and tune skills and behaviours. In the first part of the paper we introduce new concepts and results in these two areas. First, we present a cerebellum-inspired model that demonstrated efficiency in the sensory-motor control of anthropomorphic arms, and in gait control of dynamic walkers. Then, we present a set of new ideas related to robot learning, emphasizing the importance of developing teaching techniques that support learning. In the second part of the paper we propose the use in robotics of the iterative and incremental development methodologies, in the context of practical task-oriented applications. These methodologies promise to rapidly reach system-level integration, and to early identify system-level weaknesses to focus on. We apply this methodology in a task targeting the automated assembly of a modular structure using HOAP-2. We confirm this approach led to rapid development of a end-to-end capability, and offered guidance on which technologies to focus on for gradual improvement of a complete functional system. It is believed that providing Grand Challenge type milestones in practical task-oriented applications accelerates development. As a meaningful target in short-mid term we propose the 'IKEA Challenge', aimed at the demonstration of autonomous assembly of various pieces of furniture, from the box, following included written/drawn instructions.

Stoica, Adrian↗
NASA NTRS1998

On the Efficacy of Source Code Optimizations for Cache-Based Systems

Obtaining high performance without machine-specific tuning is an important goal of scientific application programmers. Since most scientific processing is done on commodity microprocessors with hierarchical memory systems, this goal of "portable performance" can be achieved if a common set of optimization principles is effective for all such systems. It is widely believed, or at least hoped, that portable performance can be realized. The rule of thumb for optimization on hierarchical memory systems is to maximize temporal and spatial locality of memory references by reusing data and minimizing memory access stride. We investigate the effects of a number of optimizations on the performance of three related kernels taken from a computational fluid dynamics application. Timing the kernels on a range of processors, we observe an inconsistent and often counterintuitive impact of the optimizations on performance. In particular, code variations that have a positive impact on one architecture can have a negative impact on another, and variations expected to be unimportant can produce large effects. Moreover, we find that cache miss rates - as reported by a cache simulation tool, and confirmed by hardware counters - only partially explain the results. By contrast, the compiler-generated assembly code provides more insight by revealing the importance of processor-specific instructions and of compiler maturity, both of which strongly, and sometimes unexpectedly, influence performance. We conclude that it is difficult to obtain performance portability on modern cache-based computers, and comment on the implications of this result.

VanderWijngaart, Rob F.↗
NASA NTRS1998

On the Efficacy of Source Code Optimizations for Cache-Based Systems

Obtaining high performance without machine-specific tuning is an important goal of scientific application programmers. Since most scientific processing is done on commodity microprocessors with hierarchical memory systems, this goal of "portable performance" can be achieved if a common set of optimization principles is effective for all such systems. It is widely believed, or at least hoped, that portable performance can be realized. The rule of thumb for optimization on hierarchical memory systems is to maximize temporal and spatial locality of memory references by reusing data and minimizing memory access stride. We investigate the effects of a number of optimizations on the performance of three related kernels taken from a computational fluid dynamics application. Timing the kernels on a range of processors, we observe an inconsistent and often counterintuitive impact of the optimizations on performance. In particular, code variations that have a positive impact on one architecture can have a negative impact on another, and variations expected to be unimportant can produce large effects. Moreover, we find that cache miss rates-as reported by a cache simulation tool, and confirmed by hardware counters-only partially explain the results. By contrast, the compiler-generated assembly code provides more insight by revealing the importance of processor-specific instructions and of compiler maturity, both of which strongly, and sometimes unexpectedly, influence performance. We conclude that it is difficult to obtain performance portability on modern cache-based computers, and comment on the implications of this result.

VanderWijngaart, Rob F.↗
NASA NTRS2001

Process Engineering Technology Center Initiative

NASA's Kennedy Space Center (KSC) is developing as a world-class Spaceport Technology Center (STC). From a process engineering (PE) perspective, the facilities used for flight hardware processing at KSC are NASA's premier factories. The products of these factories are safe, successful shuttle and expendable vehicle launches carrying state-of-the-art payloads. PE is devoted to process design, process management, and process improvement, rather than product design. PE also emphasizes the relationships of workers with systems and processes. Thus, it is difficult to speak of having a laboratory for PE at KSC because the entire facility is practically a laboratory when observed from a macro level perspective. However, it becomes necessary, at times, to show and display how KSC has benefited from PE and how KSC has contributed to the development of PE; hence, it has been proposed that a Process Engineering Technology Center (PETC) be developed to offer a place with a centralized focus on PE projects, and a place where KSC's PE capabilities can be showcased, and a venue where new Process Engineering technologies can be investigated and tested. Graphics for showcasing PE capabilities have been designed, and two initial test beds for PE technology research have been identified. Specifically, one test bed will look into the use of wearable computers with head mounted displays to deliver work instructions; the other test bed will look into developing simulation models that can be assembled into one to create a hierarchical model.

Centeno, Martha A.↗
NASA NTRS2002

Process Engineering Technology Center Initiative

NASA's Kennedy Space Center (KSC) is developing as a world-class Spaceport Technology Center (STC). From a process engineering (PE) perspective, the facilities used for flight hardware processing at KSC are NASA's premier factories. The products of these factories are safe, successful shuttle and expendable vehicle launches carrying state-of-the-art payloads. PE is devoted to process design, process management, and process improvement, rather than product design. PE also emphasizes the relationships of workers with systems and processes. Thus, it is difficult to speak of having a laboratory for PE at K.S.C. because the entire facility is practically a laboratory when observed from a macro level perspective. However, it becomes necessary, at times, to show and display how K.S.C. has benefited from PE and how K.S.C. has contributed to the development of PE; hence, it has been proposed that a Process Engineering Technology Center (PETC) be developed to offer a place with a centralized focus on PE projects, and a place where K.S.C.'s PE capabilities can be showcased, and a venue where new Process Engineering technologies can be investigated and tested. Graphics for showcasing PE capabilities have been designed, and two initial test beds for PE technology research have been identified. Specifically, one test bed will look into the use of wearable computers with head mounted displays to deliver work instructions; the other test bed will look into developing simulation models that can be assembled into one to create a hierarchical model.

Centeno, Martha A.↗
NASA NTRS2018

Tracking Components

This poster outlines the findings during a 10-week, full-time summer internship at NASA’s Stennis Space Center (SSC) in Mississippi. As an intern with RA10, the Project Management Division of Center Operations Directorate, I contributed to tasks related to the advancement of systems and operations across SSC. My main priority was to optimize the transportation process of work order kits delivered from the Michoud Assembly Facility (MAF) in New Orleans, Louisiana. An example work order kit would include instructions and materials to complete the replacement of a broken light switch. Unfortunately, kits that arrive at SSC often contain incorrect parts, which results in returning to MAF to get the necessary parts. Integrating a wireless tracking and identification system could improve this way of operating by providing a parts lists and kit location. This idea of using wireless technology will essentially cut costs, time and effort. The main objective for this summer is to develop options for affordable tracking and identification systems that can be used across the agency.

Meredith, Shelby↗
NASA NTRS1984

PASCAL/48 reference manual

PASCAL/48 is a programming language for the Intel MCS-48 series of microcomputers. In particular, it can be used with the Intel 8748. It is designed to allow the programmer to control most of the instructions being generated and the allocation of storage. The language can be used instead of ASSEMBLY language in most applications while allowing the user the necessary degree of control over hardware resources. Although it is called PASCAL/48, the language differs in many ways from PASCAL. The program structure and statements of the two languages are similar, but the expression mechanism and data types are different. The PASCAL/48 cross-compiler is written in PASCAL and runs on the CDC CYBER NOS system. It generates object code in Intel hexadecimal format that can be used to program the MCS-48 series of microcomputers. This reference manual defines the language, describes the predeclared procedures, lists error messages, illustrates use, and includes language syntax diagrams.

Knight, J. C.↗
NASA NTRS1968

Training manual on optical alignment instruments

Training Manual RQA/M5 provides a basic course of instruction in the use of optical instruments for precise dimensional control and alignment of structural elements and assemblies, such as associated with space vehicles, aircraft, ships, and buildings.

Source record↗
NASA NTRS1989

Automatic Parametric Testing Of Integrated Circuits

Computer program for parametric testing saves time and effort in research and development of integrated circuits. Software system automatically assembles various types of test structures and lays them out on silicon chip, generates sequency of test instructions, and interprets test data. Employs self-programming software; needs minimum of human intervention. Adapted to needs of different laboratories and readily accommodates new test structures. Program codes designed to be adaptable to most computers and test equipment now in use. Written in high-level languages to enhance transportability.

Jennings, Glenn A.↗
NASA NTRS1981

Teachers guide for building and operating weather satellite ground stations for high school science

A number of colleges and universities are operating APT direct readout stations. However, high school science teachers have often failed to realize the potential of meteorological satellites and their products as unique instructional tools. The ability to receive daily pictures from these satellites offers exciting opportunities for secondary school teachers and students to assemble the electronic hardware and to view real time pictures of Earth from outer space. The station and pictures can be used in the classroom to develop an approach to science teaching that could span many scientific disciplines and offer many opportunities for student research and participation in scientific processes. This can be accomplished with relatively small expenditures of funds for equipment. In most schools some of the equipment may already be available. Others can be constructed by teachers and/or students. Yet another source might be the purchase of used equipment from industry or through the government surplus channels. The information necessary for individuals unfamiliar with these systems to construct a direct readout for receiving real time APT photographs on a daily basis in the classroom is presented.

Summers, R. J.↗
NASA NTRS2007

Space Station and Shuttle Payloads: Rack Insertion Device Pneumatic Assembly Setup and Test

As part of my KSC summer internship, I was given the very cool task of writing a test preparation sheet (TPS). A TPS is a set of instructions for certain procedures or tasks, and serves as the documentation for the tasks. TPSs guide task leaders and technicians throughout the work procedures, safely, informing them of what steps will be hazardous, what precautions must be taken, and what to do in the case of an accident or emergency. I was placed in Boeing's Resupply & Return Division (R&R). R&R is responsible for sending up food and supplies to the International Space Station (ISS) with the use of three Italian Multi Purpose Logistics Modules - Leonardo, Donatello, and Raffaello. The supplies are loaded into Resupply Stowage Racks (RSRs) or Resupply Stowage Platforms (RSPs) (though, both are usually referred to as racks), depending on their size and shape. These racks are loaded into the modules with the help of a specialized crane known as the Rack Insertion Device (RID). The RID rests on four pneumatic air jacks, these allow for an operator to raise or lower the RID. The pneumatic air system supplies the air jacks with the necessary air pressure required to lift the RID.

Conde, Nathan↗
NASA NTRS1980

MBASIC processor

MBASIC is high-level, interactive computer language that reduces time of computer task programming. Outstanding features of MBASIC include: multiple assignments or statements in single instruction; conditional, assignment, and repetitive statement modifiers; and excellent string-handling capabilities. Two machine versions are available: UNIVAC (written in reentrant Assembler code for execution under EXEC 8) AND DEC-10 (written in Assembler code for execution under TOPS-10).

Hartley, R. B.↗