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Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits
As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.
Reliability of CSP assemblies with underfill subjected to 4,000 extreme temperature cycles
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Update on JPL-led CSP/SIP activities (chip scale package/systems-in-a-package)
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Qualification and Reliability for MEMS and IC Packages
Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface
Design Parameters Influencing Reliability of CCGA Assembly: A Sensitivity Analysis
Area Array microelectronic packages with small pitch and large I/O counts are now widely used in microelectronics packaging. The impact of various package design and materials/process parameters on reliability has been studied through extensive literature review. Reliability of Ceramic Column Grid Array (CCGA) package assemblies has been evaluated using JPL thermal cycle test results (-50(deg)/75(deg)C, -55(deg)/100(deg)C, and -55(deg)/125(deg)C), as well as those reported by other investigators. A sensitivity analysis has been performed using the literature da to study the impact of design parameters and global/local stress conditions on assembly reliability. The applicability of various life-prediction models for CCGA design has been investigated by comparing model's predictions with the experimental thermal cycling data. Finite Element Method (FEM) analysis has been conducted to assess the state of the stress/strain in CCGA assembly under different thermal cycling, and to explain the different failure modes and locations observed in JPL test assemblies.
A Compact, Modular Package for Superconducting Bolometer Arrays
As bolometer arrays grow to ever-larger formats, packaging becomes a more critical engineering issue. We have designed a detector package to house a superconducting bolometer array, SQUID multiplexers, bias and filtering circuitry, and electrical connectors. The package includes an optical filter, magnetic shielding, and has well-defined thermal and mechanical interfaces. An early version of this package has been used successfully in the GISMO 2mm camera, a 128-pixel camera operating at a base temperature of 270mK. A more advanced package permits operation at lower temperatures by providing direct heat sinking to the SQUIDS and bias resistors, which generate the bulk of the dissipation in the package. Standard electrical connectors provide reliable contact while enabling quick installation and removal of the package. We describe how the design compensates for differing thermal expansions, allows heat sinking of the bolometer array, and features magnetic shielding in critical areas. We highlight the performance of this detector package and describe its scalability to 1280-pixel arrays in the near future.
Assembly Reliability of Ball Grid Array and Chip Scale Packages for High Reliability Applications
Different aspects of advanced surface mount package technology have been investigated for aerospace applications. Three key areas included the assembly reliability of conventional Surface Mount, Ball Grid Arrays (BGAs), and Chip Scale Packages.
A Compact, Modular Superconducting Bolometer Array Package
We have designed a detector package to house a superconducting bolometer array, SQUID multiplexers, bias and integration circuitry, optical filtering, electrical connectors, and thermal/mechanical interfaces. This package has been used successfully in the GISMO 2mm camera, a 128-pixel camera operating at a base temperature of 270mK. Operation at lower temperatures is allowed by providing direct heat sinking to the SQUIDS and bias resistors, which generate the bulk of the dissipation in the package. Standard electrical connectors provide reliable contact while enabling quick installation and removal of the package. Careful design has gone into the compensation for differing thermal expansions, the need for heat sinking of the bolometer array, and the placement of magnetic shielding in critical areas. In this presentation, we detail the design and performance of this detector package and describe its scalability to 1280- pixel arrays in the near future.
Planetary and deep space requirements for photovoltaic solar arrays
In the past 25 years, the majority of interplanetary spacecraft have been powered by nuclear sources. However, as the emphasis on smaller, low cost missions gains momentum, the majority of missions now being planned will use photovoltaic solar arrays. This will present challenges to the solar array builders, inasmuch as planetary requirements usually differ from earth orbital requirements. In addition, these requirements often differ greatly, depending on the specific mission; for example, inner planets vs. outer planets, orbiters vs. flybys, spacecraft vs. landers, and so on. Also, the likelihood of electric propulsion missions will influence the requirements placed on solar array developers. The paper will discuss representative requirements for a range of planetary missions now in the planning stages. Insofar as inner planets are concerned, a Mercury orbiter is being studied with many special requirements. Solar arrays would be exposed to high temperatures and a potentially high radiation environment, and will need to be increasingly pointed off sun as the vehicle approaches Mercury. Identification and development of cell materials and arrays at high incidence angles will be critical to the design. Missions to the outer solar system that have been studied include a Galilean orbiter and a flight to the Kuiper belt. While onboard power requirements would be small (as low as 10 watts), the solar intensity will require relatively large array areas. As a result, such missions will demand extremely compact packaging and low mass structures to conform to launch vehicle constraints. In turn, the large are, low mass designs will impact allowable spacecraft loads. Inflatable array structures, with and without concentration, and multiband gap cells will be considered if available. In general, the highest efficiency cell technologies operable under low intensity, low temperature conditions are needed. Solar arrays will power missions requiring as little as approximately 100 watts, up to several kilowatts (at Earth) in the case of solar electric propulsion missions. Thus, mass and stowage volume minimization will be required over a range of array sizes. Concentrator designs, inflatable structures, and the combination of solar arrays with the telecommunications system have been proposed. Performance, launch vehicle constraints, an cost will be the principal parameters in the design trade space. Other special applications will also be discussed, including requirements relating to planetary landers and probes. In those cases, issues relating to shock loads on landing, operability in (possibly dusty) atmospheres, and extreme temperature cycles must be considered, in addition to performance, stowed volume, and costs.
Status of NASA Goddard Space Flight Center's Participation in SNAP
Dr. Rauscher will present programatic status and high-level/summary information on the technical status of NASA Goddard Space Flight Center's participation in the SuperNova Acceleration Probe (SNAP). Goddard's participation falls into four areas, and status in each of these will be covered. These areas are as follows: (I) focal plane array and packaging, (2) Teledyne HAWAII-4RG sensor chip assembly, (3) communications studies, and (4) integration and test studies.
SM Package Miniaturization Trends and Assembly Reliability Challenges
Different aspects of advanced surface mount package technology have been investigated. Three key areas included the assembly reliability of conventional Surface Mount (SM), Ball Grid Arrays (BGAs), and Chip Scale Packages (CSPs).
CSP/BGA Board level Reliability
Different aspects of advanced surface mount package technology have been investigated for aerospace applications. Three key areas included the assembly reliability of conventional Surface Mount, Ball Grid Arrays (BGAs), and Chip Scale Packages.
Reliability of BGA Packages for Highly Reliable Application and Chip Scale Package Board Level Reliability
Diffenent aspects of advanced surface mount package technology have been investigated for aerospace applications. Three key areas included understanding assembly reliability behavior of conventional surface Mount, Ball Grid Arrays (BGAs), and Chip Scale Packages.
Reliability and paste process optimization of eutectic and lead-free for mixed packaging
This paper reports the results of an experiment that utilized the JPL's area array consortium test vehicle design, containing a myriad of mixed technology components with an OSP finish. The details of the reliability study are presented in this paper.
Report of the sensor readout electronics panel
The findings of the Sensor Readout Electronics Panel are summarized in regard to technology assessment and recommended development plans. In addition to two specific readout issues, cryogenic readouts and sub-electron noise, the panel considered three advanced technology areas that impact the ability to achieve large format sensor arrays. These are mega-pixel focal plane packaging issues, focal plane to data processing module interfaces, and event driven readout architectures. Development in each of these five areas was judged to have significant impact in enabling the sensor performance desired for the Astrotech 21 mission set. Other readout issues, such as focal plane signal processing or other high volume data acquisition applications important for Eos-type mapping, were determined not to be relevant for astrophysics science goals.
Nano-engineered Multiwall Carbon Nanotube-copper Composite Thermal Interface Material for Efficient Heat Conduction
Efforts in integrated circuit (IC) packaging technologies have recently been focused on management of increasing heat density associated with high frequency and high density circuit designs. While current flip-chip package designs can accommodate relatively high amounts of heat density, new materials need to be developed to manage thermal effects of next-generation integrated circuits. Multiwall carbon nanotubes (MWNT) have been shown to significantly enhance thermal conduction in the axial direction and thus can be considered to be a candidate for future thermal interface materials by facilitating efficient thermal transport. This work focuses on fabrication and characterization of a robust MWNT-copper composite material as an element in IC package designs. We show that using vertically aligned MWNT arrays reduces interfacial thermal resistance by increasing conduction surface area, and furthermore, the embedded copper acts as a lateral heat spreader to efficiently disperse heat, a necessary function for packaging materials. In addition, we demonstrate reusability of the material, and the absence of residue on the contacting material, both novel features of the MWNT-copper composite that are not found in most state-of-the-art thermal interface materials. Electrochemical methods such as metal deposition and etch are discussed for the creation of the MWNT-Cu composite, detailing issues and observations with using such methods. We show that precise engineering of the composite surface affects the ability of this material to act as an efficient thermal interface material. A thermal contact resistance measurement has been designed to obtain a value of thermal contact resistance for a variety of different thermal contact materials.
A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors
In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.