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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2010

Reliability of area array packages with 1500-2500 I/Os

This report first provides a literature survey for designing, manufacturing, and reliability test results for area array packages with 1500 to 2500 inputs/outputs (I/Os). It then presents test matrix on design, yield, and workmanship defects on assembly and environmental testing, including thermal cycle and mechanical drop-test evaluation results for FCBGA1704, FPBGA432, and PBGA676 I/Os packages assembled onto printed circuit/wiring boards (PCBs/PWBs). Finally, it summarizes lessons learned from test results for assembly and environmental testing along with optical, scanning electron microscopy (SEM), and x-ray photomicrographs showing damage progress.

Ghaffarian, Reza↗
NASA NTRS2009

Reliability of recolumned area array packages

This report presents qualification guidelines developed for recolumned, high I/O ceramic column grid array (CCGA) packages assembled onto printed wiring/circuit boards (PWBs/PCBs). It includes recolumn and assembly process development for two types of CCGA packages: those with and those without interposer. Thermal cycle test results and photomicrographs showing damage progress for recolumned CCGA assemblies are documented and presented.

Ghaffarian, Reza↗
NASA NTRS2011

BOK-Underfill Optimization for FPGA Package/Assembly

Commercial-off-the-shelf area array package technologies in high-reliability versions are being considered for NASA electronic systems. These packages are prone to early failure due to the severe mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of ball interconnections decrease, susceptibility to mechanical loading and cycling fatigue grows. This report presents a summary of the body of knowledge developed for the evaluation of area array packages and is based on surveys of literature from industry and academia. For high-reliability applications, the limited data that exists will be presented. Most data from industry deals with mechanical fatigue caused by four-point bend tests, as well as from drop tests for hand-held electronics; the most recent data will be presented, along with a brief background of prior literature. Understanding the key design guidelines and failure mechanisms from past tests is critical to developing an approach that will minimize future failures. Additional specific testing enables low-risk insertion of these advanced electronic packages.

mechanical fatigue↗
NASA NTRS2010

The Assurance Challenges of Advanced Packaging Technologies for Electronics

Advances in microelectronic parts performance are driving towards finer feature sizes, three-dimensional geometries and ever-increasing number of transistor equivalents that are resulting in increased die sizes and interconnection (I/O) counts. The resultant packaging necessary to provide assemble-ability, environmental protection, testability and interconnection to the circuit board for the active die creates major challenges, particularly for space applications, Traditionally, NASA has used hermetically packaged microcircuits whenever available but the new demands make hermetic packaging less and less practical at the same time as more and more expensive, Some part types of great interest to NASA designers are currently only available in non-hermetic packaging. It is a far more complex quality and reliability assurance challenge to gain confidence in the long-term survivability and effectiveness of nonhermetic packages than for hermetic ones. Although they may provide more rugged environmental protection than the familiar Plastic Encapsulated Microcircuits (PEMs), the non-hermetic Ceramic Column Grid Array (CCGA) packages that are the focus of this presentation present a unique combination of challenges to assessing their suitability for spaceflight use. The presentation will discuss the bases for these challenges, some examples of the techniques proposed to mitigate them and a proposed approach to a US MIL specification Class for non-hermetic microcircuits suitable for space application, Class Y, to be incorporated into M. IL-PRF-38535. It has recently emerged that some major packaging suppliers are offering hermetic area array packages that may offer alternatives to the nonhermetic CCGA styles but have also got their own inspectability and testability issues which will be briefly discussed in the presentation,

Sampson, Michael J.↗
NASA NTRS2005

Reliability of CCGA and PBGA assemblies

Area Array Packages (AAPs) with 1.27 mm pitch have been the packages of the choice for commercial applications; they are now started to be implemented for use in military and aerospace applications. Thermal cycling characteristics of plastic BGA (PBGA) and CSP assemblies, because of their wide usage for commercial applications, have been extensively reported in literature. Thermal cycling represents the on-off environmental condition for most electronic products and therefore is a key factor that defines reliability.

stakes↗
NASA NTRS1997

Taguchi Experimental Design for Cleaning PWAs with Ball Grid Arrays

Ball grid arrays (BGAs), and other area array packages, are becoming more prominent as a way to increase component pin count while avoiding the manufacturing difficulties inherent in processing quad flat packs (QFPs)...Cleaning printed wiring assemblies (PWAs) with BGA components mounted on the surface is problematic...Currently, a low flash point semi-aqueous material, in conjunction with a batch cleaning unit, is being used to clean PWAs. The approach taken at JPL was to investigate the use of (1) semi-aqueous materials having a high flash point and (2) aqueous cleaning involving a saponifier.

ball grid array area array package semi-aqueous cl↗
NASA NTRS2014

Enabling More than Moore: Accelerated Reliability Testing and Risk Analysis for Advanced Electronics Packaging

For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk.

Ghaffarian, Reza↗
NASA NTRS2013

Reliability of CGA/LGA/HDI Package Board/Assembly (Revision A)

This follow-up report presents reliability test results conducted by thermal cycling of five CGA assemblies evaluated under two extreme cycle profiles, representative of use for high-reliability applications. The thermal cycles ranged from a low temperature of 55 C to maximum temperatures of either 100 C or 125 C with slow ramp-up rate (3 C/min) and dwell times of about 15 minutes at the two extremes. Optical photomicrographs that illustrate key inspection findings of up to 200 thermal cycles are presented. Other information presented include an evaluation of the integrity of capacitors on CGA substrate after thermal cycling as well as process evaluation for direct assembly of an LGA onto PCB. The qualification guidelines, which are based on the test results for CGA/LGA/HDI packages and board assemblies, will facilitate NASA projects' use of very dense and newly available FPGA area array packages with known reliably and mitigation risks, allowing greater processing power in a smaller board footprint and lower system weight.

Ghaffarian, Reza↗
NASA NTRS2012

Reliability of CGA/LGA/HDI Package Board/Assembly

This follow-up report presents reliability test results conducted by thermal cycling of five CGA assemblies evaluated under two extreme cycle profiles, representative of use for high-reliability applications. The thermal cycles ranged from a low temperature of −55°C to maximum temperatures of either 100°C or 125°C with slow ramp-up rate (3°C/min) and dwell times of about 15 minutes at the two extremes. Optical photomicrographs that illustrate key inspection findings of up to 200 thermal cycles are presented. Other information presented include an evaluation of the integrity of capacitors on CGA substrate after thermal cycling as well as process evaluation for direct assembly of an LGA onto PCB. The qualification guidelines, which are based on the test results for CGA/LGA/HDI packages and board assemblies, will facilitate NASA projects’ use of very dense and newly available FPGA area array packages with known reliably and mitigation risks, allowing greater processing power in a smaller board footprint and lower system weight.

Ghaffarian, Reza↗
NASA NTRS2008

Reliability of PWB Microvias for High Density Package Assembly

High density PWB (printed wiring board) with microvia technology is required for implementation of high density and high I/O area array packages (AAP). COTS (commercial off-the-shelf) AAP packaging technologies in high reliability versions with 1.27 mm pitch are now being considered for use in a number of NASA systems including Space Shuttle and Mars Rovers. NASA functional system designs are requiring more and more dense AAP packages and board space, which makes board microvia technology very attractive for effectively routing a large number of package inputs/outputs. However, the reliability of the fine feature microvias including via in pads is unknown for space applications. Understanding process and QA (quality assurance) indicators for reliability are important for low risk insertion of these newly available packages and PWBs. This paper presents literature search as well as test results for a high density board subjected to various thermal cycle and reflow profiles representative of tin-lead and lead-free solder reflow. Microvias sizes ranged from two to six mil with and without filling. Daisy chain microvias monitored during the test and PWBs were cross-sectioned to determine failure and locations. Optical and SEM photographs as well as resistance changes during cycling and Tg/Td (glass transition/decomposition temperature) characterisations are presented.

fill via↗
NASA NTRS1996

Area Array Technology Evaluations for Space and Military Applications

The Jet Propulsion Laboratory (JPL) is currently assessing the use of Area Array Packaging (AAP) for National Aeronautics and Space Administration (NASA) spaceflight applications. this work is being funded through NASA Headquarters, Code Q. The paper discusses background of AAP, objectives, and uses of AAP.

AAP Area Array Technology↗
NASA NTRS1994

Controlled thermal expansion printed wiring boards based on liquid crystal polymer dielectrics

Dielectric materials based on innovative Liquid Crystal Polymers (LCP's) have been used to fabricate surface mount printed wiring boards (PWB's) with a coefficient of thermal expansion matched to leadless ceramic chip carriers. Proprietary and patented polymer processing technology has resulted in self reinforcing material with balanced in-plane mechanical properties. In addition, LCP's possess excellent electrical properties, including a low dielectric constant (less than 2.9) and very low moisture absorption (less than 0.02%). LCP-based multilayer boards processed with conventional drilling and plating processes show improved performance over other materials because they eliminate the surface flatness problems of glass or aramid reinforcements. Laser drilling of blind vias in the LCP dielectric provides a very high density for use in direct chip attach and area array packages. The material is ideally suited for MCM-L and PCMCIA applications fabricated with very thin dielectric layers of the liquid crystal polymer.

Knoll, Thomas E.↗
NASA NTRS2008

Thermal Cycle Reliability and Failure Mechanisms of CCGA and PBGA Assemblies with and without Corner Staking

Area array packages (AAPs) with 1.27 mm pitch have been the packages of choice for commercial applications; they are now starting to be implemented for use in military and aerospace applications. Thermal cycling characteristics of plastic ball grid array (PBGA) and chip scale package assemblies, because of their wide usage for commercial applications, have been extensively reported on in literature. Thermal cycling represents the on-off environmental condition for most electronic products and therefore is a key factor that defines reliability.However, very limited data is available for thermal cycling behavior of ceramic packages commonly used for the aerospace applications. For high reliability applications, numerous AAPs are available with an identical design pattern both in ceramic and plastic packages. This paper compares assembly reliability of ceramic and plastic packages with the identical inputs/outputs(I/Os) and pattern. The ceramic package was in the form of ceramic column grid array (CCGA) with 560 I/Os peripheral array with the identical pad design as its plastic counterpart.

plastic ball grid array (PBGA)↗