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This is an independent study to determine the single event destructive and transient susceptibility of the Xilinx Virtex-5QV (SIRF) device. A framework for evaluating complex digital systems targeted for harsh radiation environments such as space is presented.
Report describes experimental study of use of microelectronic advanced laser scanner (MEALS) to cause single-event upsets (SEUs) in integrated logic circuits. Basic concepts of SEU testing by use of MEALS described in "Laser Scanner Tests for Single-Event Upsets" (NPO-18216), "Single-Event-Upset Laser Scanner With Optical Bias" (NPO-18217), and "More About Laser Scanner Tests for Single-Event Upsets" (NPO-18494). Study part of continuing effort to study SEU effects of ionizing radiation on such circuits and to use MEALS as relatively inexpensive SEU-prescreening laboratory apparatus serving as alternative to heavy-ion acclerator.
This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.
Critical space applications require knowledge of single event upset (SEU) susceptibility (mission survivability). Generic SEU test and analysis techniques do not provide adequate data for survivability analysis. This presentation provides information on how to: (1) Investigate (test for) SEU susceptibilities of tactical (mission specific) designs that are implemented in a SRAM-based FPGA; and (2) Analyze SEU cross-sections for use in survivability prediction.
The objective of this coarse Single Event Effect (SEE) test is to determine the suitability of the commercial Virtex-II Pro family for use in spaceflight applications. To this end, this test is primarily intended to determine any Singe Event Latchup (SEL) susceptibilities for these devices. Secondly, this test is intended to measure the level of Single Event Upset (SEU) susceptibilities and in a general sense where they occur. The coarse SEE test was performed on a commercial XC2VP7 device, a relatively small single processor version of the Virtex-II Pro. As the XC2VP7 shares the same functional block design and fabrication process with the larger Virtex-II Pro devices, the results of this test should also be applicable to the larger devices. The XC2VP7 device was tested on a commercial Virtex-II Pro development board. The testing was performed at the Cyclotron laboratories at Texas A&M and Michigan State Universities using ions of varying energy levels and fluences.
A single event upset (SEU), defined as a transient or glitch on the output of a device, and its applicability to integrated optoelectronics are discussed in the context of spacecraft design and the need for more than a bit error rate viewpoint for testing and analysis. A methodology for testing integrated optoelectronic receivers and transmitters for SEUs is presented, focusing on the actual test requirements and system schemes needed for integrated optoelectronic devices. Two main causes of single event effects in the space environment, including protons and galactic cosmic rays, are considered along with ground test facilities for simulating the space environment.
This is an independent investigation that evaluates the single event destructive and transient susceptibility of the Xilinx Kintex-UltraScale device. Design/Device susceptibility is determined by monitoring the device under test (DUT) for Single Event Transient (SET) and Single Event Upset (SEU) induced faults by exposing the DUT to a heavy ion beam. Potential Single Event Latch-up (SEL) is monitored throughout heavy-ion testing by examining device current. This device does not have embedded mitigation. Hence, user implemented mitigation is investigated using Synopsys mitigation tools.
A system using Cf-252 and associated nuclear instrumentation has determined the single-event upset (SEU) cross section versus linear energy transfer (LET) curve for several 2K x 8 static random access memories (SRAMs). The Cf-252 fission fragments pass through a thin-film organic scintillator detector (TFD) on the way to the device under test (DUT). The TFD provides energy information for each transiting fragment. Data analysis provides the energy of the individual ion responsible for each SEU; thus, separate upset cross sections can be developed for different energy and mass regions of the californium spectrum. This californium-based device is quite small and fits onto a bench top. It provides a convenient and inexpensive supplement or alternative to accelerator and high-altitude/space SEU testing.
We present a framework for evaluating complex digital systems targeted for harsh radiation environments such as space. Focus is limited to analyzing the single event upset (SEU) susceptibility of designs implemented inside Field Programmable Gate Array (FPGA) devices. Tradeoffs are provided between application-specific versus test-specific test structures.
Paper presents recent results of continuing program for increasing resistance of integrated circuits to single-event upset (SEU). Results based on study of test data for heavy-ion SEU in more than 180 different types of devices. (Some devices perform identical functions but made by different processes.) Program also examines developments in mathematical models for SEU.
This paper examines single-event upsets in advanced commercial SOI microprocessors in a dynamic mode, studying SEU sensitivity of General Purpose Registers (GPRs) with clock frequency. Results are presented for SOI processors with feature sizes of 0.18 microns and two different core voltages. Single-event upset from heavy ions is measured for advanced commercial microprocessors in a dynamic mode with clock frequency up to 1GHz. Frequency and core voltage dependence of single-event upsets in registers is discussed.
The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.
The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.
Data taken from tests involving heavy ions in the Berkeley 88 in. cyclotron being directed at low power Schottky barrier devices are reported. The tests also included trials in the Harvard cyclotron with 130 MeV protons, and at the U.C. Davis cyclotron using 56 MeV protons. The experiments were performed to study the single event upsets in MSI logic devices containing flip-flops. Results are presented of single-event upsets (SEU) causing functional degradation observed in post-exposure tests of six different devices. The effectiveness of the particles in producing SEUs in logic device functioning was found to be directly proportional to the proton energy. Shielding was determined to offer negligible protection from the particle bombardment. The results are considered significant for the design and fabrication of LS devices for space applications.
This work describes radiation testing of Actel's ProASIC Plus and Altera's Stratix-II FPGAs. The Actel Device Under Test (DUT) was a ProASIC Plus APA300-PQ208 nonvolatile, field reprogrammable device which is based on a 0.22micron flash-based LVCMOS technology. Limited investigation has taken place into flash based FPGA technologies, therefore this test served as a preliminary reference point for various SEE behaviors. The Altera DUT was a Stratix-II EP2S60F1020C4. Single Event Upset (SEU) and Single Event Latchup (SEL) were the focus of these studies. For the Actel, a latchup test was done at an effective LET of 75.0 MeV-sq cm/mg at room temperature, and no latchup was detected when irradiated to a total fluence of 1 x 10(exp 7) particles/sq cm. The Altera part was shown to latchup at room temperature.
Combining broad-beam circuit level SEU response with ion microprobe tests on single silicon germanium heterojunction bipolar transistors allows for a better understanding of the charge collection mechanisms responsible for SEU response of HBT technology.
The performance of electronic devices in a space radiation environment is often limited by susceptibility to single-event effects (SEE), total ionizing dose (TID), and displacement damage (DD). Interpreting the results of SEE, TID, and DD testing of complex devices is quite difficult given the rapidly changing nature of both technology and the related radiation issues. Radiation testing is performed to establish the sensitivities of candidate spacecraft electronics to single-event upset (SEU), single-event latchup (SEL), single-event gate rupture (SEGR), single-event burnout (SEB), single-event transients (SETs), TID, and DD effects. Knowing where to search for these test results is a valuable resource for the aerospace engineer or spacecraft design engineer. This poster is intended to be a resource tool for finding radiation test data.
The Xilinx Virtex-II Pro is a platform FPGA that embeds multiple microprocessors within the fabric of an SRAM-based reprogrammable FPGA. The variety and quantity of resources provided by this family of devices make them very attractive for spaceflight applications. However, these devices will be susceptible to single event effects (SEE), which must be mitigated. To use the Virtex-II Pro reliably in space applications, these devices must first be tested to determine if they are susceptible to single event latchup (SEL), the degree to which they are susceptible to single event upsets (SEU) and single event transients (SET), and how these effects are manifested in the device. With this information, mitigations schemes can be developed and tested that address the specific susceptiblities of these devices. This initial SEE test uses a commercial off the shelf Virtex-II Pro evaluation board, with a single processor XC2VP7 FPGA. The FPGA on this board is an acid etched device, which can be partially covered with a shield. The shield covers a portion of the logic, routing, and memory resources along with some of the RocketIO transceivers. The processor, along with a large portion of logic, routing, memory, and transceivers are left exposed. This test will be performed at the Cyclotron Laboratories at Texas A&M University and Michigan State University using ions of varying energy levels and fluencies.