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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Low-temperature (LTO) chemical vapor deposited (CVD) silicon dioxide was investigated for use as an insulator matierial in microfabriacted ion engine accelerator grids.
In this work, efficient nonlinear frequency conversion in the mid-infrared (mid-IR) region was demonstrated by a barium titanate (BTO) on a silicon-on-insulator (SOI) substrate. The BTO thin film was epitaxially grown by pulsed-laser deposition (PLD). The tensorial second order optical nonlinearity and the ferroelectric domain property of the BTO were characterized by the polarimetric mid-IR second harmonic generation (SHG) measurements. Azimuthal-dependent polarized SHG was modeled at different combinations of the nonlinear coefficient $d_{ij}$ and the domain fraction factor $ΔD^Y/ΔD^X$. Strong SHG intensity was experimentally observed over a broad spectrum at λ = 3.1 μm - 3.7 μm. A characteristic linear dependence between the SHG signal and the square of the pumping laser intensity was observed. The monolithic integration between the epitaxial BTO and the Si provides a compact platform for efficient on-chip light generation and quantum photonic technologies.
Perturbations to the effective refractive index from nanometer-scale fabrication variations in waveguide geometry plague high index-contrast photonic platforms; this includes the ubiquitous sub-micron silicon-on-insulator (SOI) process. Such variations are particularly troublesome for phase-sensitive devices, such as interferometers and resonators, which exhibit drastic changes in performance as a result of these fabrication-induced phase errors. In this Letter, we propose and experimentally demonstrate a design methodology for dramatically reducing device sensitivity to silicon width variations. We apply this methodology to a highly phase-sensitive device, the ring-assisted Mach–Zehnder interferometer (RAMZI), and show comparable performance and footprint to state-of-the-art devices, while substantially reducing stochastic phase errors from etch variations. This decrease in sensitivity is directly realized as energy savings by significantly reducing the required corrective thermal tuning power, providing a promising path toward ultra-energy-efficient large-scale silicon photonic circuits.
We present new data in the ongoing effort to bound the effect of proton angle of incidence on the single-event upset (SEU) rate in silicon-on-sapphire (SOS) and silicon-on-insulator (SOI) devices.
Electronic systems in planetary exploration missions and in aerospace applications are expected to encounter extreme temperatures and wide thermal swings in their operational environments. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of the missions. Electronic parts based on silicon-on-insulator (SOI) technology are known, based on device structure, to provide faster switching, consume less power, and offer better radiation-tolerance compared to their silicon counterparts. They also exhibit reduced current leakage and are often tailored for high temperature operation. However, little is known about their performance at low temperature. The performance of several SOI devices and mixed-signal circuits was determined under extreme temperatures, cold-restart, and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these devices for use in space exploration missions under extreme temperatures. The experimental results obtained on selected SOI devices are presented and discussed in this paper.
An overview of the growth and characterization of epitaxial insulators on semiconductors is presented. The potential applications include semiconductor-on-insulator structures, three-dimensional and/or high-density integrated circuits, optoelectronic applications such as integrated waveguides and improved gate insulators. The growth and physical characterization of epitaxial fluorides on semiconductors are discussed. Consideration is also given to the epitaxial overgrowth of epitaxial metal layers with CaF2 as well as to the formation of a novel superlattice of Ca particles in epitaxial CaF2.
Metal-Insulated-Semiconductor Field Effect Transistor /MISFET/ device uses a silicon nitride passivation layer over a thin silicon oxide layer to enhance the radiation tolerance. It is useful in electronic systems exposed to space radiation environment or the effects of nuclear weapons.
Silicon carbide on insulator is provided by bonding bulk silicon carbide to a substrate with an oxide-oxide fusion bond, followed by thinning the bulk silicon carbide as needed. A doping-selective etch for silicon carbide is used to improve thickness uniformity of the silicon carbide layer(s).
As the project titles indicate, the work focused on Group IV nanomembranes (NMs), thin functional layers, and interfaces, all with one or more dimensions at the nanoscale. The primary focus was discovery driven fundamental science. This approach led to surprising new, unexpected results that ended up being patentable and creating commercial value, but that were also high-impact science. Our effort divided into several overlapping thrusts: 1) strain engineering of NMs, via both lattice strain and externally applied strain, 2) interfaces between crystalline semiconductor NMs and other 2D sheets that are stacked or grown on each other, and 3) charge transport (electronics and optoelectronics) in thin layers, sheets, and surfaces. We accomplish these goals via 1) fabrication of new or higher-quality materials using NM approaches, 2) growth of new combinations, or 3) transfer and stacking to create new composites. The range of materials included combinations of Si, Ge, graphene, and several III-V compounds. The work has foundations in both nano- and mesoscale science.
Metal-polymer-metal and metal-polymer-silicon thin film structures analysis for polymers bulk properties and insulator-silicon interface, noting dipole-like relaxation
Abstract The rapidly increasing solar conversion efficiency (PCE) of hybrid organic–inorganic perovskite (HOIP) thin‐film semiconductors has triggered interest in their use for direct solar‐driven water splitting to produce hydrogen. However, application of these low‐cost, electronic‐structure‐tunable HOIP tandem photoabsorbers has been hindered by the instability of the photovoltaic‐catalyst‐electrolyte (PV+E) interfaces. Here, photolytic water splitting is demonstrated using an integrated configuration consisting of an HOIP/n + silicon single junction photoabsorber and a platinum (Pt) thin film catalyst. An extended electrochemical (EC) lifetime in alkaline media is achieved using titanium nitride on both sides of the Si support to eliminate formation of insulating silicon oxide, and as an effective diffusion barrier to allow high‐temperature annealing of the catalyst/TiO 2 ‐protected‐n + silicon interface necessary to retard electrolytic corrosion. Halide composition is examined in the (FA 1‐x Cs x )PbI 3 system with a bandgap suitable for tandem operation. A fill factor of 72.5% is achieved using a Spiro‐OMeTAD‐hole‐transport‐layer (HTL)‐based HOIP/n + Si solar cell, and a high photocurrent density of −15.9 mA cm −2 (at 0 V vs reversible hydrogen electrode) is attained for the HOIP/n + Si/Pt photocathode in 1 m NaOH under simulated 1‐sun illumination. While this thin‐film design creates stable interfaces, the intrinsic photo‐ and electro‐degradation of the HOIP photoabsorber remains the main obstacle for future HOIP/Si tandem PEC devices.
Dielectrics, titanium dioxides, and vapor deposition of thin films for digital metal-insulator-silicon tranducers
Two-dimensional MEMS microshutter arrays are being developed at NASA Goddard Space Flight Center for use in the near-infrared region on the Next Generation Space Telescope (NGST). The microshutter arrays are designed for the selective transmission of light with high efficiency and high contrast. The NGST environment requires cryogenic operation at 45K. Microshutter arrays are fabricated out of silicon-oxide-insulated (SOI) silicon wafers. Arrays are close-packed silicon nitride membranes with a pixel size of 100x100 microns. Individual shutters are patterned with a torsion flexure permitting shutters to open 90 degrees with a minimized mechanical stress concentration. The mechanical shutter arrays are fabricated using MEMS technologies. The processing includes a multi-layer metal deposition and patterning of shutter electrodes and magnetic pads, reactive ion etching (RE) of the front side to form shutters out of the nitride membrane, an anisotropic back-etch for wafer thinning, followed by a deep RIE (DRIE) back-etch down to the nitride shutter membrane to form frames and relieve shutters from the silicon substrate. An additional metal deposition and patterning is used to form back electrodes. Shutters are actuated using a magnetic force and latched using an electrostatic force.
Two-dimensional MEMS microshutter arrays are being developed at NASA Goddard Space Flight Center for use in the near-infrared region on the James Webb Space Telescope (JWST). The microshutter arrays are designed for the selective transmission of light with high efficiency and high contrast. The JWST environment requires cryogenic operation at 35K. Microshutter arrays are fabricated out of silicon-oxide-insulated (SOI) silicon wafers. Arrays are close-packed silicon nitride membranes with a pixel size of 100x200 p. Individual shutters are patterned with a torsion flexure permitting shutters to open 90 degrees with a minimized mechanical stress concentration. The mechanical shutter arrays are fabricated using MEMS technologies. The processing includes a multi- layer metal deposition and patterning of shutter electrodes and magnetic pads, reactive ion etching (NE) of the front side to form shutters out of the nitride membrane, an anisotropic back-etch for wafer thinning, followed by a deep RIE (DRIE) back-etch down to the nitride shutter membrane to form W e s and relieve shutters from the silicon substrate. An additional metal deposition and patterning is used to form back electrodes. Shutters are actuated using a magnetic force and latched using an electrostatic force. . . . KEYWORDS: microshutter, MEMS, RIE, DRIE, micro-optics, near inbred, space telescope
Tunneling between metal and silicon separated by thin polymer film insulator
A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.
High temperature insulating articles having improved performance characteristics are described. The articles comprise fabrics of closely woven refractory or heat resistant fibers having particles of silicon carbide dispersed at least partially through the fabric and bonded to the fibers with an emulsifiable polyethylene wax. Such articles exhibit significantly increased high temperature emittance characteristics and an improved retention of integrity and flexibility after prolonged exposure to high temperature.
Photonic integration opens the potential to reduce size, power, and cost of applications normally relegated to table- and rack-sized systems. Today, a wide range of precision, high-end, ultra-sensitive, communication and computation, and measurement and scientific applications, including atomic clocks, quantum communications, processing, and high resolution spectroscopy, are ready to make the leap from the lab to the chip. However, many of these applications operate at wavelengths not accessible to the silicon on insulator-based silicon photonics integration platform due to absorption, power handling, unwanted nonlinearities, and other factors. Next generation photonic integration will require ultra-wideband photonic circuit platforms that scale from the ultraviolet to the infrared and that offer a rich set of linear and nonlinear circuit functions as well as low loss and high power handling capabilities. This article provides an assessment of the field in ultra-wideband photonic waveguides to bring power efficient, ultra-high performance systems to the chip-scale and enable compact transformative precision measurement, signal processing, computation, and communication techniques.