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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1982

Materials characterization and fracture mechanics of a space grade dielectric silicone insulation

The present investigation is concerned with the DC 93-500 high voltage silicone insulation material employed to pot the gun and the collector end of a traveling wave tube (TWT) used on the Landsat D Satellite. The fracture mechanics behavior of the silicone resin was evaluated by measuring the slow crack velocity as a function of the opening mode of the stress intensity factor at +25 and -10 C, taking into account various uniaxial discrete strain values. It was found that the silicone resins slow crack growth is faster than that for a high voltage insulation polyurethane material at the same stress intensity factor value and room temperature.

Abdel-Latif, A. I.↗
NASA NTRS1991

Advanced silicon on insulator technology

Undoped, thin-layer silicon-on-insulator was fabricated using wafer bonding and selective etching techniques employing a molecular beam epitaxy (MBE) grown Si0.7Ge0.3 layer as an etch stop. Defect free, undoped 200-350 nm silicon layers over silicon dioxide are routinely fabricated using this procedure. A new selective silicon-germanium etch was developed that significantly improves the ease of fabrication of the bond and etch back silicon insulator (BESOI) material.

Godbey, D.↗
NASA NTRS2008

Extreme High and Low Temperature Operation of the Silicon-On-Insulator Type CHT-OPA Operational Amplifier

A new operational amplifier chip based on silicon-on-insulator technology was evaluated for potential use in extreme temperature environments. The CHT-OPA device is a low power, precision operational amplifier with rail-to-rail output swing capability, and it is rated for operation between -55 C and +225 C. A unity gain inverting circuit was constructed utilizing the CHT-OPA chip and a few passive components. The circuit was evaluated in the temperature range from -190 C to +200 C in terms of signal gain and phase shift, and supply current. The investigations were carried out to determine suitability of this device for use in space exploration missions and aeronautic applications under wide temperature incursion. Re-restart capability at extreme temperatures, i.e. power switched on while the device was soaked at extreme temperatures, was also investigated. In addition, the effects of thermal cycling under a wide temperature range on the operation of this high performance amplifier were determined. The results from this work indicate that this silicon-on-insulator amplifier chip maintained very good operation between +200 C and -190 C. The limited thermal cycling had no effect on the performance of the amplifier, and it was able to re-start at both -190 C and +200 C. In addition, no physical degradation or packaging damage was introduced due to either extreme temperature exposure or thermal cycling. The good performance demonstrated by this silicon-on-insulator operational amplifier renders it a potential candidate for use in space exploration missions or other environments under extreme temperatures. Additional and more comprehensive characterization is, however, required to establish the reliability and suitability of such devices for long term use in extreme temperature applications.

Patterson, Richard↗
NASA NTRS1988

The design of radiation-hardened ICs for space - A compendium of approaches

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

Kerns, Sherra E.↗
NASA NTRS2002

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Pain, Bedabrata↗
NASA NTRS2005

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Zheng, Xinyu↗
NASA NTRS2005

Hot-Electron Bolometer Mixers on Silicon-on-Insulator Substrates for Terahertz Frequencies

A terahertz Hot-Electron Bolometer (HEB) mixer design using device substrates based on Silicon-On-Insulator (SOI) technology is described. This substrate technology allows very thin chips (6 pm) with almost arbitrary shape to be manufactured, so that they can be tightly fitted into a waveguide structure and operated at very high frequencies with only low risk for power leakages and resonance modes. The NbTiN-based bolometers are contacted by gold beam-leads, while other beamleads are used to hold the chip in place in the waveguide test fixture. The initial tests yielded an equivalent receiver noise temperature of 3460 K double-sideband at a local oscillator frequency of 1.462 THz and an intermediate frequency of 1.4 GHz.

bolometer↗
NASA NTRS2008

Evaluation of Silicon-on-Insulator HTOP-01 Operational Amplifier for Wide Temperature Operation

Electronics capable of operation under extreme temperatures are required in many of NASA space exploration missions. Aerospace and military applications, as well as some terrestrial industries constitute environments where electronic systems are anticipated to be exposed to extreme temperatures and wide-range thermal swings. Electronics that are able to withstand and operate efficiently in such harsh environments would simplify, if not eliminate, traditional thermal control elements and their associated structures for proper ambient operation. As a result, overall system mass would be reduced, design would be simplified, and reliability would be improved. Electronic parts that are built utilizing silicon-on-insulator (SOI) technology are known to offer better radiation-tolerance compared to their conventional silicon counterparts, provide faster switching, and consume less power. They also exhibit reduced leakage current and, thus, they are often tailored for high temperature operation. These attributes make SOI-based devices suitable for use in harsh environments where extreme temperatures and wide thermal swings are anticipated. A new operational amplifier, based on silicon-on-insulator technology and geared for high temperature well-logging applications, was recently introduced by Honeywell Corporation. This HTOP-01 dual precision operational amplifier is a low power device, operates on a single supply, and has an internal oscillator and an external clocking option [1]. It is rated for operation from -55 C to +225 C with a maximum output current capability of 50 mA. The amplifier chip is designed as a 14-pin, hermetically-sealed device in a ceramic package. Table I shows some of the device manufacturer s specifications.

Patterson, Richard↗
NASA NTRS2004

Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.

single event upset (SEU)↗
NASA NTRS2008

Astable Oscillator Circuits using Silicon-on-Insulator Timer Chip for Wide Range Temperature Sensing

Two astable oscillator circuits were constructed using a new silicon-on-insulator (SOI) 555 timer chip for potential use as a temperature sensor in harsh environments encompassing jet engine and space mission applications. The two circuits, which differed slightly in configuration, were evaluated between -190 and 200 C. The output of each circuit was made to produce a stream of rectangular pulses whose frequency was proportional to the sensed temperature. The preliminary results indicated that both circuits performed relatively well over the entire test temperature range. In addition, after the circuits were subjected to limited thermal cycling over the temperature range of -190 to 200 C, the performance of either circuit did not experience any significant change.

Patterson, Richard L.↗
NASA NTRS2003

Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets (MBU) in registers and were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors was discussed.

Yoder, G. I.↗
NASA NTRS1988

Optical waveguides in oxygen-implanted buried-oxide silicon-on-insulator structures

An analysis is made of the waveguiding properties of the oxygen-implanted, buried-oxide, silicon-on-insulator structures currently being developed for use in microelectronics. It is found that in spite of the fact that the buried-oxide layer is only a few tenths of a micrometer thick, the single-crystal overlayer can support TEo guided-wave propagation, at subbandgap wavelengths, with losses due to substrate radiation leakage at or below the benchmark level of 1 dB/cm.

Kurdi, B. N.↗
NASA NTRS2008

A Temperature Sensor using a Silicon-on-Insulator (SOI) Timer for Very Wide Temperature Measurement

A temperature sensor based on a commercial-off-the-shelf (COTS) Silicon-on-Insulator (SOI) Timer was designed for extreme temperature applications. The sensor can operate under a wide temperature range from hot jet engine compartments to cryogenic space exploration missions. For example, in Jet Engine Distributed Control Architecture, the sensor must be able to operate at temperatures exceeding 150 C. For space missions, extremely low cryogenic temperatures need to be measured. The output of the sensor, which consisted of a stream of digitized pulses whose period was proportional to the sensed temperature, can be interfaced with a controller or a computer. The data acquisition system would then give a direct readout of the temperature through the use of a look-up table, a built-in algorithm, or a mathematical model. Because of the wide range of temperature measurement and because the sensor is made of carefully selected COTS parts, this work is directly applicable to the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program--Jet Engine Distributed Engine Control Task and to the NASA Electronic Parts and Packaging (NEPP) Program. In the past, a temperature sensor was designed and built using an SOI operational amplifier, and a report was issued. This work used an SOI 555 timer as its core and is completely new work.

Patterson, Richard L.↗