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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80 high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C

Patterson, Richard L.↗
NASA NTRS2009

Assessment of SOI AND Gate, Type CHT-7408, for Operation in Extreme Temperature Environments

Electronic parts based on silicon-on-insulator (SOI) technology are finding widespread applications due to their ability to operate in harsh environments and the benefits they offer as compared to their silicon counterparts. Due to their construction, they are tailored for high temperature operation and show good tolerance to radiation events. In addition, their inherent design lessens the formation of parasitic junctions, thereby reducing leakage currents, decreasing power consumption, and enhancing speed. These devices are typically rated in temperature capability from -55 C to about +225 C, and their characteristics over this temperature range are documented in data sheets. Since electronics in some of NASA space exploration missions are required to operate under extreme temperature conditions, both cold and hot, their characteristic behavior within the full temperature spectrum must be determined to establish suitability for use in space applications. The effects of extreme temperature exposure on the performance of a new commercial-off-the-shelf (COTS) SOI AND gate device were evaluated in this work. The high temperature, quad 2-inputs AND gate device, which was recently introduced by CISSOID, is fabricated using a CMOS SOI process. Some of the specifications of the CHT-7408 chip are listed in a table. By supplying a constant DC voltage to one gate input and a 10 kHz square wave into the other associated gate input, the chip was evaluated in terms of output response, output rise (t(sub r)) and fall times (tf), and propagation delays (using a 50% level between input and output during low to high (tPLH) and high to low (tPHL) transitions). The supply current of the gate circuit was also obtained. These parameters were recorded at various test temperatures between -195 C and +250 C using a Sun Systems environmental chamber programmed at a temperature rate of change of 10 C/min. In addition, the effects of thermal cycling on this chip were determined by exposing it to a total of 12 cycles between -195 C and +250 C. Following the cycling activity, measurements were performed again at the test temperatures of -195 C, +21 C, and +250 C.

Patterson, Richard↗
NASA NTRS2009

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.

Patterson, Richard↗
NASA NTRS2013

Fully Integrated, Miniature, High-Frequency Flow Probe Utilizing MEMS Leadless SOI Technology

This work focused on developing, fabricating, and fully calibrating a flowangle probe for aeronautics research by utilizing the latest microelectromechanical systems (MEMS), leadless silicon on insulator (SOI) sensor technology. While the concept of angle probes is not new, traditional devices had been relatively large due to fabrication constraints; often too large to resolve flow structures necessary for modern aeropropulsion measurements such as inlet flow distortions and vortices, secondary flows, etc. Mea surements of this kind demanded a new approach to probe design to achieve sizes on the order of 0.1 in. (.3 mm) diameter or smaller, and capable of meeting demanding requirements for accuracy and ruggedness. This approach invoked the use of stateof- the-art processing techniques to install SOI sensor chips directly onto the probe body, thus eliminating redundancy in sensor packaging and probe installation that have historically forced larger probe size. This also facilitated a better thermal match between the chip and its mount, improving stability and accuracy. Further, the leadless sensor technology with which the SOI sensing element is fabricated allows direct mounting and electrical interconnecting of the sensor to the probe body. This leadless technology allowed a rugged wire-out approach that is performed at the sensor length scale, thus achieving substantial sensor size reductions. The technology is inherently capable of high-frequency and high-accuracy performance in high temperatures and harsh environments.

Ned, Alex↗
NASA NTRS1995

Single crystal silicon filaments fabricated in SOI: A potential IR source for a microfabricated photometric CO2 sensor

The objective of this project was to design, fabricate, and test single crystal silicon filaments as potential black body IR sources for a spectrophotometric CO2 sensing microsystem. The design and fabrication of the silicon-on-insulator (SOI) filaments are summarized and figures showing the composite layout of the filament die (which contains four filaments of different lengths -- 500 microns, 1 mm, 1.5 mm and 2 mm -- and equal widths of 15 microns) are presented. The composite includes four mask layers: (1) silicon - defines the filament dimensions and contact pads; (2) release pit - defines the oxide removed from under the filament and hence, the length of the released filament; (3) Pyrex pit - defines the pit etched in the Pyrex cap (not used); and (4) metal - defines a metal pattern on the contact pads or used as a contact hole etch. I/V characteristics testing of the fabricated SOI filaments is described along with the nitride-coating procedures carried out to prevent oxidation and resistance instability.

Tu, Juliana↗
NASA NTRS2001

An Active Substrate Driver for Enabling Mixed-Voltage SOI Systems-On-A-Chip

The current trend for space application systems is towards fully integrated systems-on-a-chip. To facilitate this drive, high-voltage transistors must reside on the same substrate as low-voltage transistors. These systems must also be radiation tolerant, particularly for space missions such as the Europa Lander and Titan Explorer. SOI CMOS technology offers high levels of radiation hardness. As a result, a high-voltage lateral MOSFET has been developed in a partially-depleted (PD) SOI technology. Utilizing high voltages causes a parasitic transistor to have non-negligible effects on a circuit. Several circuit architectures have been used to compensate for the radiation induced threshold voltage shift of the parasitic back-channel transistor. However, a new architecture for high-voltage systems must be employed to bias the substrate to voltage levels insuring all parasitic transistors remain off. An active substrate driver has been developed to accomplish task. Additional information is contained in the original extended abstract.

Jackson, S. A.↗
NASA NTRS2009

A Wide Range Temperature Sensor Using SOI Technology

Silicon-on-insulator (SOI) technology is becoming widely used in integrated circuit chips for its advantages over the conventional silicon counterpart. The decrease in leakage current combined with lower power consumption allows electronics to operate in a broader temperature range. This paper describes the performance of an SOIbased temperature sensor under extreme temperatures and thermal cycling. The sensor comprised of a temperature-to-frequency relaxation oscillator circuit utilizing an SOI precision timer chip. The circuit was evaluated under extreme temperature exposure and thermal cycling between -190 C and +210 C. The results indicate that the sensor performed well over the entire test temperature range and it was able to re-start at extreme temperatures.

Patterson, Richard L.↗
NASA NTRS2010

Evaluation of COTS SiGe, SOI, and Mixed Signal Electronic Parts for Extreme Temperature Use in NASA Missions

The NASA Electronic Parts and Packaging (NEPP) Program sponsors a task at the NASA Glenn Research Center titled "Reliability of SiGe, SOI, and Advanced Mixed Signal Devices for Cryogenic Space Missions." In this task COTS parts and flight-like are evaluated by determining their performance under extreme temperatures and thermal cycling. The results from the evaluations are published on the NEPP website and at professional conferences in order to disseminate information to mission planners and system designers. This presentation discusses the task and the 2010 highlights and technical results. Topics include extreme temperature operation of SiGe and SOI devices, all-silicon oscillators, a floating gate voltage reference, a MEMS oscillator, extreme temperature resistors and capacitors, and a high temperature silicon operational amplifier.

Patterson, Richard L.↗
DOE OSTI2024

Scalable free-space photonic antennas in foundry SOI silicon photonic platforms

We present a flexible, scalable, and low-noise design scheme for coupling free-space light into a silicon-on-insulator (SOI) electronic-photonic integrated circuit. The proposed scheme utilizes arrays of grating couplers with compact, inverse-designed power combining networks to couple a distributed optical collection area to a single output waveguide, forming a photonic antenna. Fabrication density compliance is maintained regardless of the antenna size, and the collection area can be scaled while maintaining a fixed noise floor. Using experimental grating array antennas fabricated in the GF45CLO platform, we demonstrate up to a 6.7× increase in the signal-to-noise ratio (SNR) of a lens-less monolithic free-space photonic receiver using a 4×4 grating array.

Rollinson, John (ORCID:0000000157130832)↗
NASA NTRS1988

Dynamics Explorer 1 SOI images of the Antarctic ozone hole

The Dynamics Explorer (DE) satellite carries an Auroral Imaging Package which contains filters designed for performing backscatter ultraviolet measurements to measure total column ozone in the Earth's middle and lower atmosphere. Measurements are obtained at 317.5 mm (to measure ozone absorption) and 360 nm (to measure scene reflectivity). In October 1985 and 1986, measurements were obtained near apogee of the Antarctic ozone hole. The only other high spatial resolution measurements were obtained from the Nimbus 7 Total Ozone Mapping Spectrometer (TOMS) experiment. In October 1987, the Dynamics Explorer apogee had precessed into the Northern Hemisphere preventing measurements of the ozone hole. However, measurements should be obtained from DE of the ozone hole in both 1988 and 1989. Considering that the Nimbus 7 TOMS instrument has long exceeded its expected lifetime, the DE Spin Scan Ozone Imager (SOI) experiment could easily play a crucial role in studies of the ozone hole over the next few years.

Keating, G. M.↗
NASA NTRS1995

Prediction of coronal and heliospheric magnetic fields: The promise of SOI-MDI on SOHO

Models of the coronal magnetic field have been developed over the years that reproduce the static characteristics of coronal and heliospheric structures fairly well. Limitations of spatial and temporal resolution and nonuniform quality of the input data have made it particularly difficult to investigate the response of the corona to rapidly changing photospheric conditions. The Solar Oscillations Investigation (SOI) experiment on SOHO, scheduled for launch late in 1995, will produce a series of full-disk photospheric magnetic field observations with 4" resolution about every 2 hours for the next several years. Higher resolution observations of the center of the disk will be available several times per day. These data should provide a basis for predicting the coronal and heliospheric field and their changes with unprecedented accuracy during the rising phase of Solar Cycle 23.

Hoeksema, J. T.↗
NASA NTRS2003

Global and Local Helioseismic Studies of Solar Convection Zone Dynamics Using SOI-MDI on SOHO

Our joint collaborative analyses of global mode data to characterize the solar differential rotation (e.g. Thompson et al. 1996, Schou et al. 1998), and most recently to detect and analyze temporal variations in angular velocity Omega profiles both within the convection zone and in the deeper radiative interior (e.g. Howe et al 2000a,b; Toomre et al. 2000), have led to a series of fascinating discoveries. These should be pursued further as the solar cycle continues. The physical deductions being made from these studies have been greatly strengthened by utilizing both SOI-MDI and GONG data in order to have two independent observational realizations of Doppler images spanning a five-year interval, using two separate procedures to determine global mode splittings, and then analyzing those splitting data sets using both RLS and SOLA inversion procedures. There are considerable subtleties in the effects of instrumental response functions and calibrations, sensitivity of peak finding algorithms and their mode leakage estimates, and stochastic variations in mode amplitudes that can all contribute to apparent changes in the Omega profiles being inferred from sequences of helioseismic data. We have come to understand the implications of many of these calibration and analysis steps, greatly aided by frequent multi-week collaborative working sessions in our Helioseismic Analysis Facility (HAF) at JILA involving many members of the SO1 dynamics and inversion team, including most of our Co-Is during the summer months when we hold intensive working sessions. Considerable further focused attention is required in a collaborative setting on such global mode issues as we continue studying the changing sun.

Toomre, Juri↗
NASA NTRS2003

Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

Dogan, Numan S.↗