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DOE OSTI2025

Real-Time Wave Energy Converter Control Using Instantaneous Frequency

Wave Energy Converters (WECs) rely on effective Power Take-Off (PTO) control strategies to maximize energy absorption under dynamic sea conditions. Traditional hydrodynamic modeling techniques may require computationally intensive convolution calculations, making real-time control implementation challenging. This paper presents an alternative approach by leveraging instantaneous frequency estimation to dynamically adjust PTO damping in response to varying wave frequencies. Two real-time frequency estimation methods are explored: the Hilbert Transform (HT) and Phase-Locked Loop (PLL). The Hilbert Transform method provides accurate frequency tracking but introduces a delayed response due to its dependence on causal data. Conversely, the PLL approach demonstrates strong potential in frequency tracking but requires careful gain tuning, particularly in complex sea states. Comparative evaluations across multiple test cases—including sinusoidal variations, amplitude steps, frequency step changes, and real-world JONSWAP spectrum waves—highlight the strengths and limitations of each method. The two different PTO control techniques across the various frequency estimation methods were tested under real-sea states using a state-space model of a point-absorbing Wave Energy Converter. The Capture Width Ratio (CWR) is used as a performance metric, with results showing that the HT achieves a 10.6% improvement, while the PLL estimation yields a 0.9% improvement relative to the fixed parameter control baseline. These results highlight the effectiveness of real-time frequency estimation in improving energy absorption compared to static control parameters.

WEC control↗

DOE OSTI2026

Secondary-Side Active Rectifier Synchronization and Control in LCC-LC Compensated Inductive Power Transfer Systems

This paper proposes a communication-less synchronization and output power control strategy for LCC-LC compensated inductive power transfer systems with a secondaryside active rectifier. By replacing the passive rectifier with an active bridge, the proposed architecture eliminates the need for a separate secondary-side DC-DC converter and enables direct regulation of battery power. The key challenge in such a system is achieving robust synchronization of the secondary active bridge with the primary inverter without access to primary-side signals. To address this issue, the secondary-side variables are analyzed and the current through the secondary series inductor is identified as a load-independent synchronization variable with a fixed phase relationship to the primary excitation. A fixed-frequency second order generalized (SOGI)-based phase locked loop (PLL) is used to estimate the switching phase and frequency, and a phase-shift-based output power controller is developed using a phasor-transformer model of the active bridges. A modified control formulation is further introduced to remove phase-dependent loop-gain variation and simplify controller design. Simulation results validate the proposed method under both fixed and varying switching-frequency conditions, demonstrating successful frequency tracking from 82 kHz to 88 kHz and accurate output power regulation over a wide operating range. The proposed method offers a compact and effective solution for high-power IPT systems by enabling secondary-side synchronization and control without wireless communication or an additional DC-DC conversion stage.

Fernandes, Arnold Anthony [ORNL] (ORCID:0009000631↗

DOE OSTI2023

Stabilizing a strongly nonlinear structure through shaker dynamics in fixed frequency voltage control tests

Bifurcations are commonly encountered during force controlled swept and stepped sine testing of nonlinear structures, which generally leads to the so-called jump-down or jump-up phenomena between stable solutions. There are various experimental closed-loop control algorithms, such as control-based continuation and phase-locked loop, to stabilize dynamical systems through these bifurcations, but they generally rely on specialized control algorithms that are not readily available with many commercial data acquisition software packages. A recent method was developed to experimentally apply sequential continuation using the shaker voltage that can be readily deployed using commercially available software. By utilizing the stabilizing effects of electrodynamic shakers and the force dropout phenomena in fixed frequency voltage control sine tests, this approach has been demonstrated to stabilize the unstable branch of a nonlinear system with three branches, allowing for three multivalued solutions to be identified within a specific frequency bandwidth near resonance. Recent testing on a strongly nonlinear system with vibro-impact nonlinearity has revealed jumping behavior when performing sequential continuation along the voltage parameter, like the jump phenomena seen during more traditional force controlled swept and stepped sine testing. Here, this paper investigates the stabilizing effects of an electrodynamic shaker on strongly nonlinear structures in fixed frequency voltage control tests using both numerical and experimental methods. The harmonic balance method is applied to the coupled shaker-structure system with an electromechanical model to simulate the fixed voltage control tests and predict the stabilization for different parameters of the model. The simulated results are leveraged to inform the design of a set of experiments to demonstrate the stabilization characteristics on a fixture-pylon assembly with a vibro-impact nonlinearity. Through numerical simulation and experimental testing on two different strongly nonlinear systems, the various parameters that influence the stability of the coupled shaker-structure are revealed to better understand the performance of fixed frequency voltage control tests.

42 ENGINEERING↗

DOE OSTI2025

An Arbitrary Time Interval Generator Base on Vernier Clocks with 0.67 ps Adjustable Steps Implemented in FPGA

In TDC testing and timing system implementations, it is often necessary to generate signal pulses with finely adjustable time intervals. In delay cell–based schemes, the adjustment resolution is constrained by the propagation delay of the cells—typically 15–20 ps per step—and is sensitive to temperature and supply voltage variations. This document presents a fully digital approach that uses two vernier clocks, generated by two stages of cascaded phase-locked loops (PLLs) with a slight frequency difference, to achieve adjustable timing intervals through accumulated phase differences. The scheme was validated on two families of low-cost FPGA devices, achieving adjustable step sizes of 0.67 ps and 0.97 ps.

Wu, Jin-yuan [Fermilab] (ORCID:0000000344329521)↗

DOE OSTI2021

Cooperative Inverters to Overcome PLL Malfunctions

This paper presents a cooperative strategy between smart inverters to overcome instability and undesired trips of inverters caused by Phase-Locked Loop (PLL) malfunctions. For the grid-interactive inverter, PLL is typically required to measure the phase angle of the AC voltage at the Point of Common Coupling (PCC) of the inverter. Accurate phase-angle measurement is critical for grid-interactive inverters to stay synchronized with the power grid. If the inverters are interconnected through a communication link, they can support each other by sharing their grid information, such as phase-angles at their PCCs. The cooperative strategy utilizes the phase-angles and voltages at PCCs in a neighborhood to identify any possible PLL malfunctions or measurement inaccuracies and then enable the inverters to make corrective decisions. The efficacy of the cooperative strategy has been verified through simulation results in MATLAB/Simulink environment in this paper.

Sadeque, Fahmid↗

DOE OSTI2023

An Ultra-Fast Inrush-Current-Free Startup Method for Grid-tie Inverter without Voltage Sensors

This paper proposes an ultra-fast inrush-currentfree startup method for grid-tie inverters without voltage sensors and phase-locked loop (PLL). Traditionally, the grid-tie inverter needs the voltage measured from points of common couplings (PCC) to generate the phase angle via PLL for inverter pulsewidth- modulation (PWM) signals. The startup procedure is slow and inrush current occurs if the initial PWM does not match the unknown grid voltage well. This paper proposes a startup method that only uses measured inverter ac currents to generate the initial PWM by controlling the current to zero. The generated PWM pattern can be used to reproduce the real grid voltage regardless of the grid impedance. The zero-crossing points of the grid voltage are detected and then used for grid synchronization. The proposed startup procedure only needs a few cycles (16.67 ms/cycle) to reliably synchronize the inverter to the grid without any inrush current. Simulation and experimental results are presented to verify the effectiveness of this control strategy.

He, Yuchen↗

DOE OSTI2025

Oscillation Risks of Grid-Following and Grid-Forming Inverter-Based Resources in Series-Compensated Networks

Here, this paper investigates the dynamic behavior of a grid-connected inverter-based resource (IBR) when connected radially to a series compensated line. Potential interactions between the series compensation and the IBR have been identified for both types: grid-following (GFL) or grid-forming (GFM). The study begins with electromagnetic transient (EMT) simulations to demonstrate stability issues. Subsequently, nonlinear analytical models are formulated in the dq frame, validated against the EMT simulation, and leveraged to assess eigenvalues and participation factors. Influencing factors of the dominant oscillation modes have been identified. The analysis results show that series compensation may make a mode associated with the synchronization unit unstable. Furthermore, customized feedback systems are built for the synchronizing loop. Series compensation can increase the sensitivity of the voltage phase angle towards the synchronizing angle, and introduce phase lag in the real power response towards the synchronizing angle. These factors may cause interactions with the phase-locked loop in GFL-IBR systems and with power-based synchronization in GFM-IBR systems, potentially leading to instability.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2022

An Inner-Loop Control Method for the Filter-less, Voltage Sensor-less, and PLL-less Grid-Following Inverter-Based Resource

This paper presents a novel inner-loop control method for the inverter-based resource (IBR). The innovative concepts include removing the voltage sensors at the point of common coupling (PCC), removing the inverter interface inductance, and removing the traditional phase-locked loop (PLL) circuits. Simulation is conducted to verify the feasibility of the method. Furthermore, the virtual impedance is applied to the control loop to improve the current THD and dynamics. Compared to the traditional control, the proposed one helps offload the system by reducing the bulky inductors and voltage sensors without compromising the control performance.

grid-forming inverter, inner-loop control, filterl↗

DOE OSTI2022

A New Type of Weak Grid IBR Oscillations

This letter presents the discovery of a new type oscillations associated with inverter-based resources (IBRs) in weak grids. While typical weak grid oscillations become worse when the grid strength decreases and the power exporting level increases, this new type of oscillations appear when the grid becomes weaker and the power exporting level decreases. Electromagnetic transient (EMT) simulation results are presented, along with eigenvalue loci for a varying power. The notable signatures of such oscillations are also remarked. In further analysis, a feedback system consisting of two blocks is derived with one block associated with the phase-locked-loop (PLL) and the other associated with the rest of the system. Here, this feedback system quantitatively demonstrates why insufficient damping in the PLL may be an issue for stability. Open-loop analysis shows that a larger phase lag in angle tracking in the low-frequency range due to high power exporting level at the weak grid condition is beneficial to the open-loop poles introduced by the PLL. And this is the reason why such oscillations may appear when power is ramping down.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2026

PIP-II LLRF Master Oscillator and Precision Reference Line- Station Level Design and Testing

The PIP-II superconducting linac at Fermilab requires a highly stable RF Reference Line to maintain phase synchronization throughout the accelerator. Temperature-induced changes in the electrical length of long coaxial cables can introduce phase drift and measurement errors. The reference-line architecture mitigates these effects by phase averaging the forward and reflected RF signals, while a phase-locked loop anchors the system to the master oscillator. This work focuses on the characterization, validation, and mechanical integration of station-level RF assemblies using CAD modeling, vector network analyzer measurements, and spectrum analyzer testing. PID-controlled thermal plates will stabilize critical RF components and further reduce temperature-dependent phase and amplitude variations. These methods support repeatable, standardized designs that can be reliably integrated across the different reference-line stations.

Mosher, Alexander [U. Illinois, Chicago; Fermilab]↗

DOE OSTI2026

PIP-II LLRF Master Oscillator and Precision Reference Line - Station Level Design and Testing

The PIP-II superconducting linac at Fermilab requires a highly stable RF Reference Line to maintain phase syn- chronization throughout the accelerator. Temperature- induced changes in the electrical length of long coaxial cables can introduce phase drift and measurement errors. The reference-line architecture mitigates these effects by phase averaging the forward and reflected RF signals, while a phase-locked loop anchors the system to the mas- ter oscillator. This work focuses on the characterization, validation, and mechanical integration of station-level RF assemblies using CAD modeling, vector network analyzer measurements, and spectrum analyzer testing. PID-controlled thermal plates will stabilize critical RF components and further reduce temperature-dependent phase and amplitude variations. These methods sup- port repeatable, standardized designs that can be reliably integrated across the different reference-line stations.

Mosher, Alexander [U. Illinois, Chicago]↗

DOE OSTI2020

A 1.2-V 6-GHz Dual-Path Charge-Pump PLL Frequency Synthesizer for Quantum Control and Readout in CMOS 65-nm Process

This paper presents a low jitter dual-path chargepump phase locked loop (PLL) synthesizer in a CMOS 65-nm process for quantum readout applications. The PLL incorporates a programmable dual chargepump and a loop filter with both proportional and integral paths that can be driven independently providing flexible control of the loop bandwidth to achieve low jitter performance. The design is implemented at 300 K and critical blocks like voltage-controlled oscillator (VCO) and chargepump (CP) are analyzed at 77 K based on the characterized results. The LC-VCO is realized with the class-C NMOS only architecture with 5-bit coarse control and quadrature signals are generated with poly phase filter. The VCO is designed with the tuning range of 1 GHz around the center frequency of 6 GHz with Phase Noise of -123 dBc/Hz and -132 dBc/Hz at 1MHz offset at 300 K and 77 K temperature. The simulated PLL rms jitter is 125 fs at 6 GHz with a power consumption of 8 mW at the 1.2 V power supply.

47 OTHER INSTRUMENTATION↗

DOE OSTI2020

Design of a Non-PLL Grid-Forming Inverter for Smooth Microgrid Transition Operation: Preprint

This paper develops a non-phase-locked loop (PLL) grid-connected inverter that can improve the microgrid’s transients during transition operation. By emulating the operation of a synchronous machine, the inverter generates its own voltage and frequency during startup, synchronizes and connects to the grid, then operates in reactive power mode (grid-feeding) with self-generated voltage and frequency, and switches to voltage-frequency mode to establish system voltage and frequency (grid-forming) when the microgrid disconnects from the main grid, and vice versa. To enable fast synchronization, active synchronization control is adopted both during inverter startup and microgrid reconnection operation. The simulation results show that the developed non-PLL grid-connected inverter works effectively to synchronize the inverter and microgrid to the grid and avoids a phase jump during microgrid transition operation. Thus, the microgrid’s transients are significantly improved with the proposed control technique.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

DOE OSTI2025

Reinforcement Learning‐Based Adaptation of Grid Following Inverter's Internal Controller to Networked Microgrids' Strengths

The varying topological configurations, generator commitments and dispatches, and dynamic load demand lead to changing system's strengths during the operations of networked microgrids. When the system's strengths significantly change, the fixed control gains at large devices may result in unsatisfactory system performance; this necessitates the tuning of the control gains at large devices to adapt to the changing system's strengths. In this paper, observer-based reinforcement learning (RL) is utilised to automatically tune the proportional-integral (PI) gains of phase lock loop (PLL) controller of grid-following (GFL) inverters to adapt to the changing strengths of microgrids and networked microgrids. The RL agent in this framework augments an observer predicting system's strengths, from which the RL control policy will adjust accordingly to tune the PLL controller's gains towards the system's strengths. Also, to enhance the control performance, the recently introduced Barrier function-based RL framework is leveraged for the design of reward function to prevent the high frequency nadir. An operational 26 kV electric distribution system, which is modelled as networked microgrids, is used to illustrate the need and effectiveness of the proposed RL-tuned control.

frequency response↗

DOE OSTI2022

A 20 Gbps PAM4 data transmitter ASIC for particle physics experiments

We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 2$^{7}$-1 Pseudo-Random Binary Sequence (PRBS), which also serves as a frame aligner. GBS20 is tested to work at 10.24 and 20.48 Gbps with a VCSEL-based Transmitter-Optical-Subassembly (TOSA). The power consumption of GBS20 is below 238 mW and reduced to 164 mW in the low-power mode.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2022

A radiation tolerant clock generator for the CMS endcap timing layer readout chip

Here, we present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear Energy Transfer (LET) from 1.3 to 62.5 MeV × cm 2 /mg.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2025

An integer- N frequency synthesizer for flexible on-chip clock generation

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in a 65 nm CMOS process. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked to a 10–50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. In conclusion, experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.

47 OTHER INSTRUMENTATION↗

DOE OSTI2022

Grid-Forming Control Using TAPAS Software Defined Inverters

Here, this paper discusses the design and hardware implementation aspects of state-feedback primary control for grid forming inverters. The primary control consists of two tracking control laws: voltage tracking and frequency/angle tracking. The voltage tracking control requires voltage and current at the inverter's switch terminal (i.e. before the filter). The fundamental component of switch terminal voltage is estimated using the inverter's average model while the switch terminal current is estimated using an observer, thus obviating the need for sensors at the switch terminals. The measurements of frequency and angle(s) needed for frequency/angle tracking are noisy due to measurement noises and inherent delays in the phase locked loop (PLL). Conditioning of these feedback signals is discussed in detail, and the corresponding changes in the control design are provided to better attenuate the impact of noises. Effectiveness of the proposed design and implementation is demonstrated by the implementation results from TAPAS software defined inverter (SDI).

24 POWER TRANSMISSION AND DISTRIBUTION↗