Detecting and minimizing RF breakdown on microfabricated surface ion traps .
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Surface ion traps are a promising platform for quantum computing due to their potential to store large numbers of ions that can be addressed by electrical and optical control signals in order to implement quantum algorithms. Increasing the power of the quantum computer requires increasing the number of ions, but this poses a significant challenge in that it leads to a non-linear increase in on-chip power dissipation. The primary contributor to this power scaling in current devices is the capacitance between the radio frequency (RF) electrode and the metal plane that shields the silicon substrate from the RF signals applied to it. Silicon has traditionally been chosen for the substrate material for compatibility with the processing required for multi-metal-level traps. In this work, we address these capacitance and fabrication challenges by replacing the commonly used silicon substrate with an insulating sapphire substrate to fabricate a multi-metal-level ion trap, while still employing common semiconductor manufacturing techniques. This change in substrate allows the design to remove the metal shielding from the device design, reducing the capacitance of the RF electrode. The electrical characteristics of these traps were measured, specifically trap impedance, capacitance, and voltage breakdown, and compared to nearly identical silicon trap devices. Finally, we used laser cutting techniques to shape a sapphire wafer into bowtie shapes matching silicon traps previously fabricated at Sandia National Labs to explore solutions for integrating sapphire substrates into non-rectangular ion trap designs.
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An ion trap chip, which may be used for quantum information processing and the like, includes an integrated microwave antenna. The antenna is formed as a radiator connected by one of its ends to the center trace of a microwave transmission line and connected by its other end to a current return path through a ground trace of the microwave transmission line. The radiator includes several parallel, coplanar radiator traces connected in series. The radiator traces are connected such that they all carry electric current in the same direction, so that collectively, they simulate a single, unidirectionally flowing sheet of current. In embodiments, induced currents in underlying metallization planes are suppressed by parallel slots that extend in a direction perpendicular to the radiator traces.
A radio-frequency (RF) surface ion trap chip includes an RF electrode and an integrated capacitive voltage divider in which an intermediate voltage node is capacitively connected between the RF electrode and a ground. A sensor output trace is connected to the intermediate voltage node.
Disclosed herein are methods of using a fluoro oil mask to prepare a beam pen lithography pen array.
A method is provided for subtractively processing a layer of etchable material formed over an electrically conductive surface region of a workpiece. The workpiece is immersed in a liquid solution, generally but not exclusively a conductive solution, that comprises an etchant for the etchable material, so that etching of the etchable material is initiated. An electric circuit is connected to include a control electrode, a reference electrode, and the electrically conductive surface region of the workpiece. The electric circuit is used to monitor the development process dynamically at each of a plurality of intervals during the etching. The etching is terminated when the electrochemical signal satisfies a criterion indicating that the etching is complete.
Anodized aluminum oxide (AAO) has been used as nanotemplates for nanomaterials and nanodevice fabrications. Microfabrication techniques are attracting attention for nanodevice synthesis. However, AAO requires a microfabrication-compatible substrate due to its brittleness. While there are studies that already show AAO on compatible substrates, the pore sizes may not be applicable for multicomponent nanodevices. In this study, wide pore AAOs with ohmic bottom contacts are fabricated on 76 mm Si wafers. Sputtering was used to deposit Al along with supporting layers to achieve this goal. A quiescent electropolishing technique was used to smooth the surface of Al. Standard photolithography was used to define the active area on the Al for anodization. Then 195 V two-step anodization was performed to fabricate wide pore AAOs with pore diameters ranging from 130 ± 32 nm to 400 ± 31 nm with interpore distance of 480 ± 47 nm. Furthermore, it also showed that the ordering of the pores depended on the current density over the more conventional anodization time.
Abstract In the first decade of high‐velocity microparticle impact research, hardly any modification of the original experimental setup has been necessary. However, future avenues for the field require advancements of the experimental method to expand both the impact variables that can be quantitatively assessed and the materials and phenomena that can be studied. This work explores new design concepts for the launch pad (the assembly that launches microparticles upon laser ablation) that can address the root causes of many experimental challenges that may limit the technique in the future. Among the design changes contemplated, the substitution of a stiff glass launch layer for the standard elastomeric polymer layer offers a number of improvements. First, it facilitates a reduction of the gap between launch pad and target from hundreds to tens of micrometers and thus unlocks a reproducibility in targeting a specific impact location better than the diameter of the test particle itself (±1.75 µm for SiO 2 particles 7.38 µm in diameter). Second, the inert glass surface enables experiments at higher temperatures than previously possible. Finally—as demonstrated by the launch of thin‐film Au disks—a launch pad made of materials standard in microfabrication paves the way to facile microfabrication of advanced impactors.