Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “Memory device”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Zoned namespaces for computing device main memory

Disclosed in some examples are methods, systems, memory devices, memory controllers, and machine-readable mediums which provide for reserving physical memory device resources to specific execution units. Execution units may include processes, threads, virtual machines, functions, procedures, or the like. Physical memory device resources may include channels, modules, ranks, banks, bank groups, and the like. For example, a physical memory device resource that is reservable may be a smallest unit that allows for parallel access with another of the same size unit.

Sheridan, Patrick Michael↗
NASA NTRS1998

Analysis of a Memory Device Failure

The recent failure of a vintage memory device presented a unique challenge to failure analysts. Normally device layouts, fabrication parameters and other technical information were available to assist the analyst in the analysis. However, this device was out of production for many years and the manufacturer was no longer in business, so the information was not available. To further complicate this analysis, the package leads were all but removed making additional electrical testing difficult. Under these conditions, new and innovative methods were used to analyze the failure. The external visual exam, radiography, PIND, and leak testing were performed with nominal results. Since electrical testing was precluded by the short lead lengths, the device was delidded to expose the internal structures for microscopic examination. No failure mechanism was identified. The available electrical data suggested an ESD or low level EOS type mechanism which left no visible surface damage. Due to parallel electrical paths, electrical probing on the chip failed to locate the failure site. Two non-destructive Scanning Electron Microscopy techniques, CIVA (Charge Induced Voltage Alteration) and EBIC (Electron Beam Induced Current), and a liquid crystal decoration technique which detects localized heating were employed to aid in the analysis. CIVA and EBIC isolated two faults in the input circuitry, and the liquid crystal technique further localized two hot spots in regions on two input gates. Removal of the glassivation and metallization revealed multiple failure sites located in the gate oxide of two input transistors suggesting machine (testing) induced damage.

Nicolas, David P.↗
NASA NTRS1968

Multilayer plated wire shows promise as memory device

Multilayer plated wire memory system surpasses planar thin film memories because of its high speed, simplicity, and high output. The device consists of 5 mil Be-Cu wire plated with Ni-Fe alloy about 1 micron thick crossed orthogonally by word lines.

Kadish, D.↗
NASA NTRS1974

Intermediate memory devices

Several methods of transfer and processing of data whose practical implementation requires operational memory devices are described. Devices incorporating multistable elements are proposed and their main parameters are given. The possibility of using the proposed devices for storing information for transmission in space radio communications channels is examined.

Basalayev, G. V.↗
NASA NTRS1973

Measurement of irregularities in angular velocities of rotating assemblies in memory devices on magnetic carriers

Problems in measurement of irregularities in angular velocity of rotating assemblies in memory devices with rigid and flexible magnetic data carriers are discussed. A device and method for determination of change in angular velocities in various frequency and rotation rate ranges are examined. A schematic diagram of a photoelectric sensor for recording the signal pulses is provided. Mathematical models are developed to show the amount of error which can result from misalignment of the test equipment.

Virakas, G. I.↗
NASA NTRS1993

Comparison of single event upset rates for microelectronic memory devices during interplanetary solar particle events

Variability in the methods and models used for single event upset calculations in microelectronic memory devices can lead to a range of possible upset rates. Using heavy ion and proton data for selected DRAM and SRAM memories, we have calculated an array of upset rates in order to compare the Adams worst case interplanetary solar flare model to a model proposed by scientists at the Jet Propulsion Laboratory. In addition, methods of upset rate calculation are compared: the Cosmic Ray Effects on Microelectronics CREME code and a Monte Carlo algorithm developed at the Applied Physics Laboratory. The results show that use of a more realistic, although still conservative, model of the space environment can have significant cost saving benefits.

Mckerracher, P. L.↗
NASA NTRS1994

Partial-Thickness Grooves In A VBL Memory Device

Bias magnetic fields tailored to match those needed elsewhere in device. Grooves through part of thickness of magnetic garnet storage layer of vertical-Bloch-line (VBL) memory device used to confine magnetic bubble and stripe domains in desired storage areas. VBL-memory concept described in "Vertical-Bloch-Line Memory" (NPO-18467).

Katti, Romney R.↗
DOE OSTI2021

Ion beam etching dependence of spin-orbit torque memory devices with switching current densities reduced by Hf interlayers

We report on the fabrication of nanoscale, three-terminal in-plane spin–orbit torque switching devices with low switching current densities. Critical parameters in the fabrication process, including the ion beam etching angle and time, were optimized to avoid fabrication defects and improve device yield. Measurements of the magnetic field and current-induced switching behavior of the tunnel junctions demonstrate a sensitivity to the nanopillar aspect ratio, which dictates the nanopillars’ anisotropy and thermal stability. Additionally, we show that the current density required for switching can be reduced and the device thermal stability increased by inserting Hf interlayers into the heterostructure. Micromagnetic simulations are generally consistent with the experimentally observed switching behavior, suggesting an increase in the interfacial perpendicular anisotropy at the CoFeB/MgO interface and the reduction in the Dzyaloshinskii–Moriya interaction at the W/CoFeB interface by the Hf interlayers.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Electron Doping-Induced Metal–Insulator Transition in LaNiO 3 and Memory Devices

LaNiO 3 (LNO) is the only rare-earth nickelate that does not undergo a temperature-driven insulator-metal transition. Here, we report the successful deposition of epitaxial LNO thin films on LaAlO 3 substrates by a chemical solution deposition method. We report a metal-insulator transition driven by electron doping from hydrogen using catalytic Pd electrodes. A series of in-plane devices with LNO thin films and Pd-Au as the two working terminals were designed and fabricated by photolithography. Further, we report their resistance switching behavior and synaptic multiresistance states under voltage pulses. The results demonstrate the universality of electron doping-driven phase transitions in the rare-earth nickelates and their relevance to emerging memory and computing technologies.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1975

Open coil structure for bubble-memory-device packaging

Concept has several important advantages over close-wound system: memory and coil chips are separate and interchangeable; interconnections in coil level are eliminated by packing memory chip and electronics in single structure; and coil size can be adjusted to optimum value in terms of power dissipation and field uniformity.

Chen, T. T.↗
NASA NTRS1990

Fast, Capacious Disk Memory Device

Device for recording digital data on, and playing back data from, memory disks has high recording or playback rate and utilizes available recording area more fully. Two disks, each with own reading/writing head, used to record data at same time. Head on disk A operates on one of tracks numbered from outside in; head on disk B operates on track of same number in sequence from inside out. Underlying concept of device applicable to magnetic or optical disks.

Muller, Ronald M.↗
DOE OSTI2024

Controlling reversible phase transitions in rare-earth nickelates for novel memory devices

Resistive switching in correlated complex oxides is lucrative for emerging applications in neuromorphic computing, and densely scaled non-volatile memory. Electrical conductance of such complex oxides can be controllable switched across multiple orders of magnitude by either (a) electroforming a conduction channel (e.g., in tungsten oxide), or (b) inducing Mott-Hubbard transition (e.g., in rare-earth nickelates)– both via controlled migration of defects (such as oxygen vacancies) under applied bias. Nevertheless, the promise of such defect-driven electronic transitions are far from realized due to a lack of fundamental understanding of the atomic-scale processes that underlie migration and spatiotemporal evolution of oxygen vacancies over nano-to-mesoscopic length/timescales under applied electric field. In this project, we employ a synergistic integration of density functional theory (DFT) calculations, ab initio/classical molecular dynamics (AIMD/CMD) simulations, machine learning (ML), precision synthesis, and multi-modal X-ray imaging experiments to address this knowledge gap. Such an integrated approach offers to elucidate the correlations between subtle structural distortion and oxidation states; treat localized charge carriers; describe defect/ion transport in the presence of electric field; and, in turn, greatly advance the current understanding of microstructural evolution in complex oxides under applied bias. The fundamental knowledge gained from this work will enable precise control over hierarchical defect structures and unravel new routes to manipulate resistance states in complex oxides. This, in turn, will accelerate design of novel devices with desired set of neural functionalities, and high-speed densely-scaled resistive random access memory technologies.

36 MATERIALS SCIENCE↗