SEARCH · Engineering Papers

Results for “CIRCUIT”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2

All sources NASA NTRS DOE OSTI

DOE OSTI2020

HEMP Testing of Substation Yard Circuit Breaker Control and Protective Relay Circuits

There are concerns about the effects of High-Altitude Electromagnetic Pulses (HEMP) on the electric power grid. Activities to date tested and analyzed vulnerability of digital protective relays (DPRs) used in power substations, but the effect of HEMP on the greater substation environment is not well known. This work establishes a method of testing the vulnerability of circuit breaker control and protective relay circuits to the radiated E1 pulse associated with HEMP based on coupling to the cables in a substation yard. Two DPRs from Schweitzer Engineering Laboratories, Inc. were independently tested. The test setup also included a typical cable in a substation yard with return plane to emulate the ground grid and other ground conductors near the yard cable, cabinetry housing the installed DPRs, station battery and battery charger, terminal block elements, and a breaker simulator to emulate a substation yard configuration. The DPRs were powered from the station battery and the transformer inputs energized with a three-phase source to maintain typical operating conditions during the tests. Vulnerability testing consisted of a conducted E1 pulse injected into the center of the yard cable of the DPR circuits. Current measurements on the yard cable and DPR inputs indicated significant attenuation of the conducted pulse arriving at the control house equipment from the emulated substation yard. This reduction was quantified with respect to the equivalent open-circuit voltage on the yard cable. No equipment damage or undesired operation occurred on the tested circuits for values below 180 kV, which is significantly higher than the anticipated coupling to a substation yard cable.

24 POWER TRANSMISSION AND DISTRIBUTION↗

NASA NTRS1990

Statistical circuit design for yield improvement in CMOS circuits

This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

Kamath, H. J.↗

NASA NTRS2016

Method and Circuit for Injecting a Precise Amount of Charge onto a Circuit Node

A method and circuit for injecting charge into a circuit node, comprising (a) resetting a capacitor's voltage through a first transistor; (b) after the resetting, pre-charging the capacitor through the first transistor; and (c) after the pre-charging, further charging the capacitor through a second transistor, wherein the second transistor is connected between the capacitor and a circuit node, and the further charging draws charge through the second transistor from the circuit node, thereby injecting charge into the circuit node.

Hancock, Bruce R.↗

DOE OSTI2018

Test circuits for integrated circuit counterfeit detection

Described herein are various technologies pertaining to identifying counterfeit integrated circuits (ICs) by way of allowing the origin of fabrication to be verified. An IC comprises a main circuit and a test circuit that is independent of the main circuit. The test circuit comprises at least one ring oscillator (RO) signal that, when energized, is configured to output a signal that is indicative of a semiconductor fabrication facility where the IC was manufactured.

42 ENGINEERING↗

DOE OSTI2019

Test circuits for integrated circuit counterfeit detection

Helinski, Ryan↗

DOE OSTI2020

Three-terminal magnetic tunnel junction synapse circuits with spike-timing-dependent plasticity.

Abstract not provided.

Akinola, Otitoaleke↗

DOE OSTI2024

Quantum Circuit Partitioning for Scalable Noise-Aware Quantum Circuit Re-Synthesis

Re-synthesis techniques are utilized to optimize the quantum circuit. To enable scalable re-synthesis a divide-and-conquer approach is adopted that partitions the circuit into smaller blocks, which are optimized independently. Several algorithms have been proposed to minimize the block number while maximizing the gate count of each block. However, they vary in their performance and may not yield the highest output fidelity. We propose a reinforcement learning-based quantum circuit partitioning framework that incorporates the physical properties of the quantum hardware to maximize the output fidelity post-quantum circuit optimization. To accelerate the training, we also propose a noise injection method that enables on-the-fly optimization in the reinforcement learning environment, independent of the adopted optimization/re-synthesis method at the block level. We evaluate our approach compared to different partitioning techniques using various quantum benchmarks executed on IBM Q Hanoi quantum computer.

Charrwi, Mohammad Walid↗

NASA NTRS1991

An Investigative Redesign of the ECG and EMG Signal Conditioning Circuits for Two-fault Tolerance and Circuit Improvement

An investigation was undertaken to make the elctrocardiography (ECG) and the electromyography (EMG) signal conditioning circuits two-fault tolerant and to update the circuitry. The present signal conditioning circuits provide at least one level of subject protection against electrical shock hazard but at a level of 100 micro-A (for voltages of up to 200 V). However, it is necessary to provide catastrophic fault tolerance protection for the astronauts and to provide protection at a current level of less that 100 micro-A. For this study, protection at the 10 micro-A level was sought. This is the generally accepted value below which no possibility of microshock exists. Only the possibility of macroshock exists in the case of the signal conditioners. However, this extra amount of protection is desirable. The initial part deals with current limiter circuits followed by an investigation into the signal conditioner specifications and circuit design.

Obrien, Edward M.↗

NASA NTRS2011

Fast-responding short circuit protection system with self-reset for use in circuit supplied by DC power

A short circuit protection system includes an inductor, a switch, a voltage sensing circuit, and a controller. The switch and inductor are electrically coupled to be in series with one another. A voltage sensing circuit is coupled across the switch and the inductor. A controller, coupled to the voltage sensing circuit and the switch, opens the switch when a voltage at the output terminal of the inductor transitions from above a threshold voltage to below the threshold voltage. The controller closes the switch when the voltage at the output terminal of the inductor transitions from below the threshold voltage to above the threshold voltage.

Burns, Bradley M.↗

DOE OSTI2019

Bootstrapping circuit and unipolar logic circuits using the same

Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits.

Sun, Xaio↗

DOE OSTI2017

An Algorithm of an X-ray Hit Allocation to a Single Pixel in a Cluster and Its Test-Circuit Implementation

An on-chip implementable algorithm for allocation of an X-ray photon imprint, called a hit, to a single pixel in the presence of charge sharing in a highly segmented pixel detector is described. Its proof-of-principle implementation is also given supported by the results of tests using a highly collimated X-ray photon beam from a synchrotron source. The algorithm handles asynchronous arrivals of X-ray photons. Activation of groups of pixels, comparisons of peak amplitudes of pulses within an active neighborhood and finally latching of the results of these comparisons constitute the three procedural steps of the algorithm. A grouping of pixels to one virtual pixel, that recovers composite signals and event driven strobes, to control comparisons of fractional signals between neighboring pixels are the actuators of the algorithm. The circuitry necessary to implement the algorithm requires an extensive inter-pixel connection grid of analog and digital signals, that are exchanged between pixels. A test-circuit implementation of the algorithm was achieved with a small array of 32 × 32 pixels and the device was exposed to an 8 keV highly collimated to a diameter of 3-μm X-ray beam. Furthermore, the results of these tests are given in this paper assessing physical implementation of the algorithm.

47 OTHER INSTRUMENTATION↗

DOE OSTI2018

Context Dependence of Biological Circuits

It has been an ongoing scientific debate whether biological parameters are conserved across experimental setups with different media, pH values, and other experimental conditions. Our work explores this question using Bayesian probability as a rigorous framework to assess the biological context of parameters in a model of the cell growth controller in You et al. When this growth controller is uninduced, the E. coli cell population grows to carrying capacity; however, when the circuit is induced, the cell population growth is regulated to remain well below carrying capacity. This growth control controller regulates the E. coli cell population by cell to cell communication using the signaling molecule AHL and by cell death using the bacterial toxin CcdB. To evaluate the context dependence of parameters such as the cell growth rate, the carrying capacity, the AHL degradation rate, the leakiness of AHL, the leakiness of toxin CcdB, and the IPTG induction factor, we collect experimental data from the growth control circuit in two different media, at two different pH values, and with several induction levels. We define a set of possible context dependencies that describe how these parameters may differ with the experimental conditions and we develop mathematical models of the growth controller across the different experimental contexts. We then determine whether these parameters are shared across experimental contexts or whether they are context dependent. For each of these possible context dependencies, we use Bayesian inference to assess its plausibility and to estimate the parameters of the growth controller. Ultimately, we find that there is significant experimental context dependence in this circuit. Furthermore, we also find that the estimated parameter values are sensitive to our assumption of a context relationship.

59 BASIC BIOLOGICAL SCIENCES↗

DOE OSTI2014

Compact lumped circuit model of discharges in DC accelerator using partial element equivalent circuit

DC Accelerators undergoes different types of discharges during its operation. A model depicting the discharges has been simulated to study the different transient conditions. The paper presents a Physics based approach of developing a compact circuit model of the DC Accelerator using Partial Element Equivalent Circuit (PEEC) technique. The equivalent RLC model aids in analyzing the transient behavior of the system and predicting anomalies in the system. The electrical discharges and its properties prevailing in the accelerator can be evaluated by this equivalent model. A parallel coupled voltage multiplier structure is simulated in small scale using few stages of corona guards and the theoretical and practical results are compared. The PEEC technique leads to a simple model for studying the fault conditions in accelerator systems. Compared to the Finite Element Techniques, this technique gives the circuital representation. The lumped components of the PEEC are used to obtain the input impedance and the result is also compared to that of the FEM technique for a frequency range of (0-200) MHz. (author)

43 PARTICLE ACCELERATORS↗

NASA NTRS1972

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

Source record↗

NASA NTRS2008

Circuit with a Switch for Charging a Battery in a Battery Capacitor Circuit

A circuit for charging a battery combined with a capacitor includes a power supply adapted to be connected to the capacitor, and the battery. The circuit includes an electronic switch connected to the power supply. The electronic switch is responsive to switch between a conducting state to allow current and a non-conducting state to prevent current flow. The circuit includes a control device connected to the switch and is operable to generate a control signal to continuously switch the electronic switch between the conducting and non-conducting states to charge the battery.

Stuart, Thomas A.↗

DOE OSTI2014

Tunable power law in the desynchronization events of coupled chaotic electronic circuits

We study the statistics of the amplitude of the synchronization error in chaotic electronic circuits coupled through linear feedback. Depending on the coupling strength, our system exhibits three qualitatively different regimes of synchronization: weak coupling yields independent oscillations; moderate to strong coupling produces a regime of intermittent synchronization known as attractor bubbling; and stronger coupling produces complete synchronization. In the regime of moderate coupling, the probability distribution for the sizes of desynchronization events follows a power law, with an exponent that can be adjusted by changing the coupling strength. Such power-law distributions are interesting, as they appear in many complex systems. However, most of the systems with such a behavior have a fixed value for the exponent of the power law, while here we present an example of a system where the exponent of the power law is easily tuned in real time.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2020

GaN‐based split phase transformer‐less PV inverter with auxiliary ZVT circuit

This paper explores performance enhancement of the common ground dynamic dc‐link (CGDL) inverter for single phase photovoltaic (PV) applications by a combination of gallium nitride (GaN) devices, split phase topology, coupled inductors, and zero voltage transition (ZVT) scheme. The CGDL inverter has the inherent advantage of minimised dc‐link capacitance and negligible leakage current due to the common ground configuration, but its reported efficiency was usually lower because of the higher dc‐link voltage used for the reduction of decoupling capacitance to a great extent. To solve the efficiency problem, in this study, a soft switching circuit is proposed for the first stage, while a coupled inductor integrated magnetics is incorporated in the second stage to reduce inductor loss, volume, and cost. Both of these topological improvements combined with the use of GaN devices facilitate in achieving high efficiency without compromising converter power density. Extensive experimental results are provided from a GaN based 1 kVA hardware prototype to demonstrate the superior performance of the CGDL inverter attaining a peak efficiency of 98.7% and a California Energy Commission efficiency of 98.5% at 75/50 kHz switching frequency.

Xia, Yinglai↗

DOE OSTI2022

Autonomous Microgrid Restoration Using Grid-Forming Inverters and Smart Circuit Breakers

The proliferation of distributed inverter-based resources (IBRs) raises the questions if these IBRs can be used to blackstart microgrids and distribution feeders after major outages. In this paper, we propose and evaluate an autonomous microgrid restoration concept using grid-forming (GFM) IBRs and smart circuit creakers (SCBs). The concept is first explored in simulation platform and then a hardware testbed containing actual GFM inverters is developed to demonstrate these functionalities. A combination of dispatchable virtual oscillator control (dVOC) and droop-based control schemes have been designed for GFM inverter controls in the software simulations and hardware testbed. Subsequently, operation of SCBs using two distinct principles have been demonstrated that can restore or connect portions of the network.

black start↗