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All sourcesNASA NTRSDOE OSTI
NASA NTRS2010

Advanced Flip Chips in Extreme Temperature Environments

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Ramesham, Rajeshuni↗
NASA NTRS2003

Development of a 1K x 1K GaAs QWIP Far IR Imaging Array

In the on-going evolution of GaAs Quantum Well Infrared Photodetectors (QWIPs) we have developed a 1,024 x 1,024 (1K x1K), 8.4-9 microns infrared focal plane array (FPA). This 1 megapixel detector array is a hybrid using the Rockwell TCM 8050 silicon readout integrated circuit (ROIC) bump bonded to a GaAs QWIP array fabricated jointly by engineers at the Goddard Space Flight Center (GSFC) and the Army Research Laboratory (ARL). The finished hybrid is thinned at the Jet Propulsion Lab. Prior to this development the largest format array was a 512 x 640 FPA. We have integrated the 1K x 1K array into an imaging camera system and performed tests over the 40K-90K temperature range achieving BLIP performance at an operating temperature of 76K (f/2 camera system). The GaAs array is relatively easy to fabricate once the superlattice structure of the quantum wells has been defined and grown. The overall arrays costs are currently dominated by the costs associated with the silicon readout since the GaAs array fabrication is based on high yield, well-established GaAs processing capabilities. In this paper we will present the first results of our 1K x 1K QWIP array development including fabrication methodology, test data and our imaging results.

Jhabvala, M.↗
NASA NTRS2012

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

Vasile, Stefan↗
NASA NTRS2013

Mitigation of Adverse Effects Caused by Shock Wave Boundary Layer Interactions Through Optimal Wall Shaping

It is known that the adverse effects of shock wave boundary layer interactions in high speed inlets include reduced total pressure recovery and highly distorted flow at the aerodynamic interface plane (AIP). This paper presents a design method for flow control which creates perturbations in geometry. These perturbations are tailored to change the flow structures in order to minimize shock wave boundary layer interactions (SWBLI) inside supersonic inlets. Optimizing the shape of two dimensional micro-size bumps is shown to be a very effective flow control method for two-dimensional SWBLI. In investigating the three dimensional SWBLI, a square duct is employed as a baseline. To investigate the mechanism whereby the geometric elements of the baseline, i.e. the bottom wall, the sidewall and the corner, exert influence on the flow's aerodynamic characteristics, each element is studied and optimized separately. It is found that arrays of micro-size bumps on the bottom wall of the duct have little effect in improving total pressure recovery though they are useful in suppressing the incipient separation in three-dimensional problems. Shaping sidewall geometry is effective in re-distributing flow on the side wall and results in a less distorted flow at the exit. Subsequently, a near 50% reduction in distortion is achieved. A simple change in corner geometry resulted in a 2.4% improvement in total pressure recovery.

Liou, May-Fun↗
NASA NTRS2003

Integrated Electrode Arrays for Neuro-Prosthetic Implants

Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.

Brandon, Erik↗
NASA NTRS2003

Toward the Development of Group III-V Photodetectors and Imaging Arrays

A collaboration between researchers at NASA Goddard Space Flight Center (GSFC) (Code 718.1) and the Johns Hopkins University Applied Physics Laboratory (APL) on the development of gallium nitride (GaN) based photodetectors has been in existence since July 1994. This collaboration, based on APL undertaking the material growth and GSFC undertaking the device processing, has led to discrete GaN photoconductive detectors with superior characteristics to those of similar devices reported in the literature and, more recently, to the development of state-of-the art 256x256 imaging arrays with the pixels indium bump-bonded to a silicon readout circuit (RIOC). The object of this proposal is to continue the collaboration for the period 1998-2002 by outlining a program of work at the APL on the metalorganic chemical vapor deposition (MOCVD) growth of GaN and related materials for UV detector applications. In particular, emphasis will be placed on the optimization of growth on 2 in diameter substrates, on the growth of In(sub x)Ga(1-x)N and Al(sub x)Ga(1-x)N alloy structures to produce devices with a wider range of tailored cut-off wavelengths, and on the growth of pn-junction structures for photovoltaic devices.

Wickenden, Dennis K.↗
NASA NTRS2011

Infrared-Bolometer Arrays with Reflective Backshorts

Integrated circuits that incorporate square arrays of superconducting-transition- edge bolometers with optically reflective backshorts are being developed for use in image sensors in the spectral range from far infrared to millimeter wavelengths. To maximize the optical efficiency (and, thus, sensitivity) of such a sensor at a specific wavelength, resonant optical structures are created by placing the backshorts at a quarter wavelength behind the bolometer plane. The bolometer and backshort arrays are fabricated separately, then integrated to form a single unit denoted a backshort-under-grid (BUG) bolometer array. In a subsequent fabrication step, the BUG bolometer array is connected, by use of single-sided indium bump bonding, to a readout device that comprises mostly a superconducting quantum interference device (SQUID) multiplexer circuit. The resulting sensor unit comprising the BUG bolometer array and the readout device is operated at a temperature below 1 K. The concept of increasing optical efficiency by use of backshorts at a quarter wavelength behind the bolometers is not new. Instead, the novelty of the present development lies mainly in several features of the design of the BUG bolometer array and the fabrication sequence used to implement the design. Prior to joining with the backshort array, the bolometer array comprises, more specifically, a square grid of free-standing molybdenum/gold superconducting-transition-edge bolometer elements on a 1.4- m-thick top layer of silicon that is part of a silicon support frame made from a silicon-on-insulator wafer. The backshort array is fabricated separately as a frame structure that includes support beams and contains a correspond - ing grid of optically reflective patches on a single-crystal silicon substrate. The process used to fabricate the bolometer array includes standard patterning and etching steps that result in the formation of deep notches in the silicon support frame. These notches are designed to interlock with the support beams on the backshort-array structure to provide structural support and precise relative positioning. The backshort-array structure is inserted in the silicon support frame behind the bolometer array, and the notches in the frame serve to receive the support beams of the backshort-array structure and thus determine the distance between the backshort and bolometer planes. The depth of the notches and, thus, the distance between the backshort and bolometer planes, can be tailored to a value between 25 to 300 m adjusting only a few process steps. The backshort array is designed so as not to interfere with the placement of indium bumps for subsequent indium bump-bonding to the multiplexing readout circuitry

Miller, Timothy M.↗
NASA NTRS2008

MEMS Microshutter Array System for James Webb Space Telescope

A complex MEMS microshutter array system has been developed at NASA Goddard Space Flight Center (GSFC) for use as a multi-object aperture array for a Near-Infrared Spectrometer (NIRSpec). The NIRSpec is one of the four major instruments carried by the James Webb Space Telescope (JWST), the next generation of space telescope after the Hubble Space Telescope retires. The microshutter arrays (MSAs) are designed for the selective transmission of light with high efficiency and high contrast. It is demonstrated in Figure 1 how a MSA is used as a multiple object selector in deep space. The MSAs empower the NIRSpec instrument simultaneously collect spectra from more than 100 targets therefore increases the instrument efficiency 100 times or more. The MSA assembly is one of three major innovations on JWST and the first major MEMS devices serving observation missions in space. The MSA system developed at NASA GSFC is assembled with four quadrant fully addressable 365x171 shutter arrays that are actuated magnetically, latched and addressed electrostatically. As shown in Figure 2, each MSA is fabricated out of a 4' silicon-on-insulator (SOI) wafer using MEMS bulk-micromachining technology. Individual shutters are close-packed silicon nitride membranes with a pixel size close to 100x200 pm (Figure 3). Shutters are patterned with a torsion flexure permitting shutters to open 90 degrees with a minimized mechanical stress concentration. In order to prevent light leak, light shields are made on to the surrounding frame of each shutter to cover the gaps between the shutters and the Game (Figure 4). Micro-ribs and sub-micron bumps are tailored on hack walls and light shields, respectively, to prevent sticktion, shown in Figures 4 and 5. JWST instruments are required to operate at cryogenic temperatures as low as 35K, though they are to be subjected to various levels of ground tests at room temperature. The shutters should therefore maintain nearly flat in the entire temperature range between 35K and 300K. Through intensive numerical simulations and experimental studies, an optically opaque and electrically conductive metal-nitride thin film was selected as a coating material deposited on the shutters with the best thermal-expansion match to silicon nitride - the shutter blade thin film material. A shutter image shown in Figure 6 was taken at room temperature, presenting shutters slightly bowing down as expected. Shutters become flat when the temperature decreases to 35K. The MSAs are then bonded to silicon substrates that are fabricated out of 6" single-silicon wafers in the thickness of 2mm. The bonding is conducted using a novel single-sided indium flip-chip bonding technology. Indium bumps fabricated on a substrate are shown in Figure 7. There are 180,000 indium bumps for bonding a flight format MSA array to its substrate. Besides a MSA, each substrate houses five customer-designed ASIC (Application Specific Integrated Circuit) multiplexer/address chips for 2-dimensional addressing, twenty capacitors, two temperature sensors, numbers of resistors and all necessary interconnects, as shown in Figure 8. Complete MSA quadrant assemblies have been successfully manufactured and fully functionally tested. The assemblies have passed a series of critical reviews required by JWST in satisfying all the design specifications. The qualification tests cover programmable 2-D addressing, life tests, optical contrast tests, and environmental tests including radiation, vibration, and acoustic tests. A 2-D addressing pattern with 'ESA' letters programmed in a MSA is shown in Figure 9. The MSAs passed 1 million cycle life tests and achieved high optical contrast over 10,000. MSA teams are now making progress in final fabrication, testing and assembly (Figure 10). The delivery of flight-format MSA system is scheduled at the end of 2008 for being integrated to the focal plane of the NIRSpec detectors.

Li, Mary J.↗
NASA NTRS1987

Method of fabricating a PbS-PbSe IR detector array

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Barrett, John R.↗
NASA NTRS1986

PbS-PbSe IR detector arrays

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chipping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Barrett, John R.↗
NASA NTRS1989

Future directions for NICMOS arrays

The Near Infrared Camera and Multi-Object Spectrometer (NICMOS) for the Hubble Space Telescope (HST) requires focal plane arrays of 256x256 pixels for both its cameras and its spectrometers. The new arrays, developed by the Rockwell Corporation for NICMOS, have 40 microns pixels of HgCdTe bump bonded to a switched MOSFET readout. Expected read noise and dark current for the arrays at 60 K are 30 e and 1 e/sec. respectively. The basis for these numbers is previous experience with 128x128 arrays.

Thompson, R.↗
DOE OSTI2021

Dark matter microhalos from simplified models

Here, we introduce simplified models for enhancements in the matter power spectrum at small scales and study their implications for dark matter substructure and gravitational observables. These models capture the salient aspects of a variety of early Universe scenarios that predict enhanced small-scale structure, such as axionlike particle dark matter, light vector dark matter, and epochs of early matter domination. We use a model-independent, semianalytic treatment to map bumps in the matter power spectrum to early forming subsolar mass dark matter halos and estimate their evolution, disruption, and contribution to the substructure of clusters and galaxies at late times. We discuss the sensitivity of gravitational observables, including pulsar timing arrays and caustic microlensing, to both the presence of bumps in the power spectrum and variations in their basic properties.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS2009

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

imagers↗
NASA NTRS2018

Fabrication of a Hybrid Transition Edge Sensor Array for Lynx

Lynx is a proposed NASA X-Ray telescope flight mission aimed at achieving state-of-the-art angular and energy resolution with a 100 kilopixel array to probe the hot energetic young universe in unprecedented detail. To achieve these goals, our team plans on leveraging our current work in development of the focal plane for the Athena X-Ray Integral Field Unit (X-IFU) while advancing the state-of-the-art in transition edge sensor (TES) X-ray detector technology. The TES is an optimal technology for achieving both high energy and fine angular resolution at the same time because pixel features can be made extremely small and the absorber which dominates the heat capacity can be tuned to meet resolution requirements. Specifically, the proposed mission concept calls for a hybrid detector of three different arrays fabricated in the same planar process in one focal plane and optimized for different science goals. The main arrays consist of 5x5 hydras, 25 pixels of 4 micron thick Au absorbers each with a different thermal link to one common TES. The outer array has absorbers on a 50-micron pitch for most of the 5 arc-minute field-of-view, and the inner array has 25-micron absorbers for the central 1 arc-minute region. A high resolution array consisting of single pixel 1 micron thick Au absorbers on 50-micron pitch will lie off to the side. Reading out an array of this magnitude will likely require improvements in indium bump bonding to superconducting flexible wiring. Fabrication of absorbers of two different sizes requires electroplating through a photoresist mold by careful tuning of the current density to achieve uniform flat absorbers on a fine pitch scale, followed by ion milling to yield narrow streets separating the pixels while preserving high quantum efficiency. We report on progress made at fabricating the hybrid array with different absorber sizes and thicknesses. Further, we also report on ongoing work to adequately heat sink the pixels with backside wire bonding and copper coating. We also report on work to improve detector pixel yield and top side indium bump bonding to flexible wiring.

Focal plane array↗
DOE OSTI2020

Performance of a Front End prototype ASIC for picosecond precision time measurements with LGAD sensors

For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region, to mitigate the effects of the increased pile-up. The chosen detection technology is Low Gain Avalanche Detector (LGAD) silicon sensors that can provide an excellent timing resolution below 50 ps. The front-end read-out ASIC must exploit the large signal derivative and small noise provided by the sensor, while keeping low power consumption. This paper presents the results on the first prototype of a front-end ASIC, named ALTIROC0, which contains the analog stages (preamplifier and discriminator) of the read-out chip. The ASIC was characterised both alone and as part of a module with a 2×2 LGAD array of 1.1×1.1 mm 2 pads bump-bonded to it. The various contributions of the electronics to the time resolution were investigated in test-bench measurements with a calibration setup. Both when the ASIC is alone or with a bump-bonded sensor, the jitter of the ASIC is better than 20 ps for an injected charge of 10 fC. The time walk effect, which arises from the different preamplifier response for various injected charges, can be corrected up to 10 ps using a Time Over Threshold measurement. The combined performance of the ASIC and the LGAD sensor, which was measured during a beam test campaign in October 2018 with pions of 120 GeV energy at the CERN SPS, is around 40 ps for all measured modules. All tested modules show good efficiency and time resolution uniformity.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2008

Instrument Performance of GISMO, a 2 Millimeter TES Bolometer Camera used at the IRAM 30 m Telescope

In November of 2007 we demonstrated a monolithic Backshort-Under-Grid (BUG) 8x16 array in the field using our 2 mm wavelength imager GISMO (Goddard IRAM Superconducting 2 Millimeter Observer) at the IRAM 30 m telescope in Spain for astronomical observations. The 2 mm spectral range provides a unique terrestrial window enabling ground-based observations of the earliest active dusty galaxies in the universe and thereby allowing a better constraint on the star formation rate in these objects. The optical design incorporates a 100 mm diameter silicon lens cooled to 4 K, which provides the required fast beam yielding 0.9 lambda/D pixels. With this spatial sampling, GISMO will be very efficient at detecting sources serendipitously in large sky surveys, while the capability for diffraction limited imaging is preserved. The camera provides significantly greater detection sensitivity and mapping speed at this wavelength than has previously been possible. The instrument will fill in the spectral energy distribution of high redshift galaxies at the Rayleigh-Jeans part of the dust emission spectrum, even at the highest redshifts. Here1 will we present early results from our observing run with the first fielded BUG bolometer array. We have developed key technologies to enable highly versatile, kilopixel, infrared through millimeter wavelength bolometer arrays. The Backshort-Under-Grid (BUG) array consists of three components: 1) a transition-edge-sensor (TES) based bolometer array with background-limited sensitivity and high filling factor, 2) a quarter-wave reflective backshort grid providing high optical efficiency, and 3) a superconducting bump-bonded large format Superconducting Quantum Interference Device (SQUID) multiplexer readout. The array is described in more detail elsewhere (Allen et al., this conference). In November of 2007 we demonstrated a monolithic 8x 16 array with 2 mm-pitch detectors in the field using our 2 mm wavelength imager GISMO (Goddard IRAM Superconducting 2 Millimeter Observer) at the IRAM 30 m telescope in Spain for astronomical observations. The 2 mm spectral range provides a unique terrestrial window enabling ground-based observations of the earliest active dusty galaxies in the universe and thereby allowing a better constraint on the star formation rate in these objects. The optical design incorporates a 100 mm diameter silicon lens cooled to 4 K, which provides the required fast beam yielding 0.9 lambda1D pixels. With this spatial sampling, GISMO will be very efficient at detecting sources serendipitously in large sky surveys, while the capability for diffraction limited imaging is preserved. The camera provides significantly greater detection sensitivity and mapping speed at this wavelength than has previously been possible. The instrument will fill in the spectral energy distribution of high redshift galaxies at the Rayleigh-Jeans part of the dust emission spectrum, even at the highest redshifts. Here I will we present early results from our observing run with the first fielded BUG bolometer array.

Staguhn, Johannes↗
NASA NTRS1989

Hybrid Infrared Imager

Experimental device has low noise and high uniformity. Infrared imaging device combines array of InSb photodetectors with array of silicon field-effect-transistor switches. InSb chip forms roof over Si chip, each InSb detector cell engaging indium bump on corresponding Si switch cell below it. FET switches in 128-by-128 array turn on in sequence, read out charges on 128-by-128 array of photodetectors and multiplex them in serial output that represents pattern of light on array of photodetectors. Useful in sensitive infrared cameras for astronomy, medicine, inspection, and military surveillance. Reads out image data at rates up to 10 MHz and expands to 256-by-256 array.

Bailey, Gary C.↗
NASA NTRS1995

Solid-state image sensor with focal-plane digital photon-counting pixel array

A photosensitive layer such as a-Si for a UV/visible wavelength band is provided for low light level imaging with at least a separate CMOS amplifier directly connected to each PIN photodetector diode to provide a focal-plane array of NxN pixels, and preferably a separate photon-counting CMOS circuit directly connected to each CMOS amplifier, although one row of counters may be time shared for reading out the photon flux rate of each diode in the array, together with a buffer memory for storing all rows of the NxN image frame before transfer to suitable storage. All CMOS circuitry is preferably fabricated in the same silicon layer as the PIN photodetector diode for a monolithic structure, but when the wavelength band of interest requires photosensitive material different from silicon, the focal-plane array may be fabricated separately on a different semiconductor layer bump-bonded or otherwise bonded for a virtually monolithic structure with one free terminal of each diode directly connected to the input terminal of its CMOS amplifier and digital counter for integration of the photon flux rate at each photodetector of the array.

Fossum, Eric R.↗