Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “Separation circuit”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 343 records · Page 19
All sourcesNASA NTRSDOE OSTI
NASA NTRS2007

Scaling and Systems Considerations in Pulsed Inductive Thrusters

Performance scaling in pulsed inductive thrusters is discussed in the context of previous experimental studies and modeling results. Two processes, propellant ionization and acceleration, are interconnected where overall thruster performance and operation are concerned, but they are separated here to gain physical insight into each process and arrive at quantitative criteria that should be met to address or mitigate inherent inductive thruster difficulties. The effects of preionization in lowering the discharge energy requirements relative to a case where no preionization is employed, and in influencing the location of the initial current sheet, are described. The relevant performance scaling parameters for the acceleration stage are reviewed, emphasizing their physical importance and the numerical values required for efficient acceleration. The scaling parameters are then related to the design of the pulsed power train providing current to the acceleration stage. The impact of various choices in pulsed power train and circuit topology selection are reviewed, paying special attention to how these choices mitigate or exacerbate switching, lifetime, and power consumption issues.

Polzin, Kurt A.↗
NASA NTRS2003

Parallel Subconvolution Filtering Architectures

These architectures are based on methods of vector processing and the discrete-Fourier-transform/inverse-discrete- Fourier-transform (DFT-IDFT) overlap-and-save method, combined with time-block separation of digital filters into frequency-domain subfilters implemented by use of sub-convolutions. The parallel-processing method implemented in these architectures enables the use of relatively small DFT-IDFT pairs, while filter tap lengths are theoretically unlimited. The size of a DFT-IDFT pair is determined by the desired reduction in processing rate, rather than on the order of the filter that one seeks to implement. The emphasis in this report is on those aspects of the underlying theory and design rules that promote computational efficiency, parallel processing at reduced data rates, and simplification of the designs of very-large-scale integrated (VLSI) circuits needed to implement high-order filters and correlators.

Gray, Andrew A.↗
NASA NTRS1991

Memory implications of the spin-value effect in soft multilayers

New multilayer permalloy materials with thin separation layers that have significantly increased M-R coefficients at room temperature have the potential for substantially increasing both the speed and density of M-R memories. An analysis in the following discussion shows that the bit density at a given performance level is related to the product of M-R response and sheet resistivity when operating at the current-density limit. With a doubling of both sheet resistivity and M-R response over existing materials, the bit area can be reduced by about a factor of 4. Alternatively, if the bit area is kept the same, signal output is increased by a factor of 4 and circuit time constants can be reduced by a factor of 16.

Pohm, A. V.↗
NASA NTRS2019

Experimental Study on Mitigation of Lifetime-Limiting Dielectric Cracking in Extreme Temperature 4H-SiC JFET Integrated Circuits

While NASA Glenn Research Center's "Generation 10" 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100- and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si3N4 layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.

Spry, D. J.↗
NASA NTRS1982

Laser velocimeter applications to high-lift research

The application of the Lockheed-Georgia 2-D laser velocimeter (LV) burst-counter system to the flow field around a 2- and 3-element high-lift airfoil is discussed. The characteristic behavior of the confluent boundary layer (that is, the boundary layer existing downstream of a slot as it approaches and undergoes separation is evaluated. In this application, the LV represents all ideal instruments for nonintrusively probing into the narrow slots and cove areas characterizing mechanical high-lift systems. The work is being performed in the Lockheed-Georgia 10 x 30-inch low-speed test facility using a 9-inch (basic) chord section of the general aviation GAW-1 airfoil. The LV system employs a 4-W argon laser and operates in an off-axis, backscatter mode with a focus length of about 30 inches. Smoke is used as the seeding medium and is injected downstream of the model such that particle uniformity and size are constant upon completion of the tunnel circuit into the test area. The LV system is fully automated by utilizing a MAC-16 minicomputer for positioning, data acquisition, and preliminary data reduction.

Whipkey, R. R.↗
NASA NTRS2006

MMIC DHBT Common-Base Amplifier for 172 GHz

Figure 1 shows a single-stage monolithic microwave integrated circuit (MMIC) power amplifier in which the gain element is a double-heterojunction bipolar transistor (DHBT) connected in common-base configuration. This amplifier, which has been demonstrated to function well at a frequency of 172 GHz, is part of a continuing effort to develop compact, efficient amplifiers for scientific instrumentation, wide-band communication systems, and radar systems that will operate at frequencies up to and beyond 180 GHz. The transistor is fabricated from a layered structure formed by molecular beam epitaxy in the InP/InGaAs material system. A highly doped InGaAs base layer and a collector layer are fabricated from the layered structure in a triple mesa process. The transistor includes two separate emitter fingers, each having dimensions of 0.8 by 12 m. The common-base configuration was chosen for its high maximum stable gain in the frequency band of interest. The input-matching network is designed for high bandwidth. The output of the transistor is matched to a load line for maximum saturated output power under large-signal conditions, rather than being matched for maximum gain under small-signal conditions. In a test at a frequency of 172 GHz, the amplifier was found to generate an output power of 7.5 mW, with approximately 5 dB of large-signal gain (see Figure 2). Moreover, the amplifier exhibited a peak small-signal gain of 7 dB at a frequency of 176 GHz. This performance of this MMIC single-stage amplifier containing only a single transistor represents a significant advance in the state of the art, in that it rivals the 170-GHz performance of a prior MMIC three-stage, four-transistor amplifier. [The prior amplifier was reported in "MMIC HEMT Power Amplifier for 140 to 170 GHz" (NPO-30127), NASA Tech Briefs, Vol. 27, No. 11 (November 2003), page 49.] This amplifier is the first heterojunction- bipolar-transistor (HBT) amplifier built for medium power operation in this frequency band. The performance of the amplifier as measured in the aforementioned tests suggests that InP/InGaAs HBTs may be superior to high-electron-mobility (HEMT) transistors in that the HBTs may offer more gain per stage and more output power per transistor.

Paidi, Vamsi↗
NASA NTRS2006

Promoted-Combustion Chamber with Induction Heating Coil

An improved promoted-combustion system has been developed for studying the effects of elevated temperatures on the flammability of metals in pure oxygen. In prior promoted-combustion chambers, initial temperatures of metal specimens in experiments have been limited to the temperatures of gas supplies, usually near room temperature. Although limited elevated temperature promoted-combustion chambers have been developed using water-cooled induction coils for preheating specimens, these designs have been limited to low-pressure operation due to the hollow induction coil. In contrast, the improved promoted-combustion chamber can sustain a pressure up to 10 kpsi (69 MPa) and, through utilization of a solid induction coil, is capable of preheating a metal specimen up to its melting point [potentially in excess of 2,000 F (approximately equal to 1,100 C)]. Hence, the improved promoted combustion chamber makes a greater range of physical conditions and material properties accessible for experimentation. The chamber consists of a vertical cylindrical housing with an inner diameter of 8 in. (20.32 cm) and an inner height of 20.4 in. (51.81 cm). A threaded, sealing cover at one end of the housing can be unscrewed to gain access for installing a specimen. Inlet and outlet ports for gases are provided. Six openings arranged in a helical pattern in the chamber wall contain sealed sapphire windows for viewing an experiment in progress. The base of the chamber contains pressure-sealed electrical connectors for supplying power to the induction coil. The connectors feature a unique design that prevents induction heating of the housing and the pressure sealing surfaces; this is important because if such spurious induction heating were allowed to occur, chamber pressure could be lost. The induction coil is 10 in. (25.4 cm) long and is fitted with a specimen holder at its upper end. At its lower end, the induction coil is mounted on a ceramic base, which affords thermal insulation to prevent heating of the base of the chamber during use. A sapphire cylinder protects the coil against slag generated during an experiment. The induction coil is energized by a 6-kW water-cooled power supply operating at a frequency of 400 kHz. The induction coil is part of a parallel-tuned circuit, the tuning of which is used to adjust the coupling of power to the specimen. The chamber is mounted on a test stand along with pumps, valves, and plumbing for transferring pressurized gas into and out of the chamber. In addition to multiple video cameras aimed through the windows encircling the chamber, the chamber is instrumented with gauges for monitoring the progress of an experiment. One of the gauges is a dual-frequency infrared temperature transducer aimed at the specimen through one window. Chamber operation is achieved via a console that contains a computer running apparatus-specific software, a video recorder, and real-time video monitors. For safety, a blast wall separates the console from the test stand.

Richardson, Erin↗
NASA NTRSDate not supplied

Feasibility of Self Powered Actuation for Flow, Separation and Vibration Control

Gas turbine engines are anywhere from 40-50% efficient with a large amount of waste heat production. The primary focus of this work was to evaluate the feasibility of harvesting energy from sections of an imaginary but representative gas turbine engine that has large thermal gradients using thermoelectric generators (TEGs) and using the harvested energy locally for flow control using either plasma actuators or piezoelectric actuators. This work is a summary of a two- year NASA Center Innovation Fund Project from 2010 to 2012. The trade-off between thermoelectric harvesting and turbine blade surface temperature was studied to ensure that blade durability is not adversely impacted by embedding a low thermal conductivity TEG. Calculations show that at least 2-3 Watts can be harvested per blade depending on flow conditions and on the thermoelectric material chosen while maintaining metal temperatures below critical limits. BiTe and SiGe were considered as TEG materials although higher ZT materials are now in development. A circuit to convert the DC power output of the TEG to AC input for plasma actuation was fabricated and tested. Several novel plasma actuator configurations were also tested.

Thermoelectric↗
NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗
NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗
NASA NTRS1988

Development and verification of NASA Standard Initiator-2 (NSI-2)

The results of verification testing under NASA Contract NAS9-17249 are summarized in this Final Report. An Appendix is published separately. The report contains a brief discussion of design elements, test results, and a discussion of the latter. The contract was awarded for development and demonstration of design modifications to the NASA Standard Initiator-1 (NSI-1), resulting in the development of NSI-2. The intent of the project was to develop and prove the following design features: (1) Protection from premature initiation due to electrostatic potential by means other than a spark gap; (2) Development of an integral insulated charge cup for use with a zirconium/potassium perchlorate type mixture; (3) Improved cost and reliability figures by the use of a deposited ridge; and (4) Elimination of dudding as a result of the pyrotechnic shock effect, the movement of the primer composition away from the bridge circuit.

Corbin-Roberts, Linda↗
NASA NTRS2004

Strongly-Refractive One-Dimensional Photonic Crystal Prisms

One-dimensional (1D) photonic crystal prisms can separate a beam of polychromatic electromagnetic waves into constituent wavelength components and can utilize unconventional refraction properties for wavelength dispersion over significant portions of an entire photonic band rather than just near the band edges outside the photonic band gaps. Using a ID photonic crystal simplifies the design and fabrication process and allows the use of larger feature sizes. The prism geometry broadens the useful wavelength range, enables better optical transmission, and exhibits angular dependence on wavelength with reduced non-linearity. The properties of the 1 D photonic crystal prism can be tuned by varying design parameters such as incidence angle, exit surface angle, and layer widths. The ID photonic crystal prism can be fabricated in a planar process, and can be used as optical integrated circuit elements.

Ting, David Z.↗
NASA NTRS1992

Microwave properties of peeled HEMT devices sapphire substrates

The focus of this research is to demonstrate the first full radio frequency characterization of high electron mobility transistor (HEMT) device parameters. The results of this research are used in the design of circuits with peeled HEMT devices, e.g. 10 GHz amplifiers. Devices were fabricated using two HEMT structures grown by molecular beam epitaxy methods. A 500 A AlAs release layer for 'peel off' was included under the active layers of the structure. The structures are a homogeneously doped Al(0.3)GA(0.7)As/GaAs and a delta doped square well Al(.23)Ga(.77)As/GaAs HEMT structure. Devices were fabricated using a mesa isolation process. Contacts were done by sequentially evaporating Au/Ge/Au/Ni/Au followed by rapid thermal anneal at 400 C for 15 seconds. Gates were wet etch recessed and 1 to 1.4 micron Ti/Au gate metal was deposited. Devices were peeled off the GaAs substrate using Apiezon wax to support the active layer and a HF:DI (1:10) solution to remove the AlAs separation layer. Devices were then attached to sapphire substrates using van der Waals bonding.

Young, Paul G.↗
NASA NTRS1980

Effect of gravitational overloads, hypokinesia and hypodynamia on the vessels of the pulmonary blood circuit

Vessels of the pulmonary circuit are studied under normal conditions, in exposure to single stress or continuous threshold endurable chestspine gravitational stresses, and one to eight weak hypokinesia and hypodynamic effects followed by stress. Examination methods include rentgenography and microrentgenography, clearing, and histology. In exposure to gravitational stress the distal portions of the arterial vessels of the 3 and 4 orders constrict, while all veins dilate. Sinuosity of all vessels is noted. The volume of the capillary bed increases and signs of perivascular edema occur. Due to hypokinesia and hypodynamia the arteries constricted and the arterial bed becomes poor. The veins of all orders dilate and the volume of the capillary bed increases. The changes grew greater the longer the terms of hypodyamic effects. Successive combination of hypokinesia and hypodynamia and gravitational stresses cause more pronounced changes than separate effects of these two factors and result in great deformity of the vascular walls, including their rupture and penetration of formed elements beyond the limits of the vascular bed.

Kasimtsev, A. A.↗
NASA NTRS2007

Design of an Integrated-System FARAD Thruster

Pulsed inductive plasma accelerators are spacecraft propulsion devices in which energy is stored in a capacitor and then discharged through an inductive coil. The device is electrodeless, inducing a current s heet in a plasma located near the face of the coil. The propellant is accelerated and expelled at a high exhaust velocity (order of 10 km/s) through the interaction of the plasma current and the induced magne tic field, The Faraday Accelerator with RF-Assisted Discharge (FARAD) thruster is a type of pulsed inductive plasma accelerator in which t he plasma is preionized by a mechanism separate from that used to for m the current sheet and accelerate the gas. Employing a separate preionization mechanism allows for the formation of an inductive current s heet at much lower discharge energies and voltages than those used in previous pulsed inductive accelerators like the Pulsed Inductive Thr uster (PIT). In this paper, we present the design of a benchtop FARAD thruster with all the subsystems (mass injection, preionization, and acceleration) integrated into a single unit. Design of the thruster follows the guidelines and similarity performance parameters presented elsewhere. The system is designed to use the ringing, RF-frequency s ignal produced by a discharging Vector Inversion Generator (VIG) to p reionize the gas. The acceleration stage operates on the order of 100 J/pulse and can be driven by several different pulsed powertrains. These include a simple capacitor coupled to the system, a Bernardes and Merryman configuration, and a pulsecompression circuit that takes a temporally broad, low current pulse and transforms it into a short, h igh current pulse. A set of applied magnetic field coils are integrated into the system to guide the preionized propellant as it spreads ov er the face of the inductive acceleration coil. The coils are operate d in a pulsed mode, and the thruster can be operated without using the coils to determine if there is a performance improvement gain realiz ed when an applied field is present.

Polzin, K.A.↗
NASA NTRS1970

Skylab Operations Handbook: Orbital Workshop (OWS), Airlock Module (AM), Multiple Docking Adapter (MDA): Systems Descriptions - Volume 1

The Skylab Program consists of three low-earth-orbit missions of the Orbital Assembly (OA) (figure 1.0-1), extending over.an a-month period. The OA consists of the CSM docked to the Saturn Workshop.(SWS). This handbook describes the systems for three of the four major components of the SWS (OWS, AM, and MDA), and also discusses significant interfaces with the Instrument Unit (IU), ATM, and CSM. The other major component of the SWS, the ATM, is treated separately in its own handbook. The OWS, AM, MDA, ATM Deployment Assembly (ATM-DA), Fixed Airlock Shroud (FAS), Payload Shroud (PS), and IU are addressed throughout this document as individual modules from a structural standpoint only. Although normally considered a part of the launch vehicle, the IU is treated in this document as part of the SWS because of its function in preparing the SWS for orbital operation. Section 1.0 describes vehicle and mission configurations of the Skylab program and provides general descriptions of the various systems. Section 2.0 provides detailed systems data covering system interfaces, functional description, subsystems and major components description, component operation, failure modes, performance and design data, operational limitations and restrictions, and instrumentation, and briefly outlines the experiments. Section 3.0 contains illustrations of all panels and identifies the controls and displays, panels, reference designators, nomenclature, functions, circuit breakers, and power sources. The Table of Contents lists in order of appearance all sections, subsections, major paragraphs, illustrations, and tables and provides their respective page locations. Appendix A defines the abbreviations and acronyms employed throughout this handbook, and Appendix B explains the symbols used. Appendix C is a locator index that references component controls contained in Section 3.0. Appendix D is an alphabetical index of paragraph headings, illustrations, and tables, according to the key word, with applicable page numbers. Additional items of significance to the user have been included in the index. The technical level to which this document is written assumes the reader to have general knowledge of engineering terms and principles.

West, W. D.↗
NASA NTRS2003

Micro-Detection System for Determination of the Biotic or Abiotic Origin of Amino Acids

The research carried out under this PIDDP involves the development of a breadboard version of a spacecraft-based system for the detection of amino acid chirality (molecular handedness) on solar system bodies. Chirality provides an unambiguous way of distinguishing between abiotic and biotic origins since only one mirror-image form is used in the functional molecules of life. Recent advances in a variety of nano-fabrication technologies have resulted in concepts for enabling miniaturized chemical and biological analytical systems. These are complete application-specific systems that integrate fluid micro handling systems for extracting and reacting target molecules, micro-separation technologies for enhanced sensitivity and resolution, and advanced detection technologies. This effort makes use of a relatively new technology that shows demonstrated promise for spacecraft-based amino acid analysis: microchip-based capillary electrophoresis (μCE). The μCE system is capable of analyzing the type of amino acids present as well as the relative amounts of their mirror image forms. The system we developed will be able to chirally resolve all of the major amino acids found in extraterrestrial material (Gly, Ala, Val, Pro, Asp, Glu, a-aminoisobutyric acid, and isovaline) at sub-part-per-billion levels. The -CE analysis requires that the amino acids be extracted from the sample and derivatized for either optical or electrochemical detection. In our implementation, the amino acids are released from the sample by sublimation and prepared for μCE analysis using a microfluidic circuit. In addition, we have investigated the use of a microfluidic circuit for the release of amino acids from samples in which sublimation has proven to be problematic.

Jeffrey L Bada↗
NASA NTRS2012

Flexible Architecture for FPGAs in Embedded Systems

Commonly, field-programmable gate arrays (FPGAs) being developed in cPCI embedded systems include the bus interface in the FPGA. This complicates the development because the interface is complicated and requires a lot of development time and FPGA resources. In addition, flight qualification requires a substantial amount of time be devoted to just this interface. Another complication of putting the cPCI interface into the FPGA being developed is that configuration information loaded into the device by the cPCI microprocessor is lost when a new bit file is loaded, requiring cumbersome operations to return the system to an operational state. Finally, SRAM-based FPGAs are typically programmed via specialized cables and software, with programming files being loaded either directly into the FPGA, or into PROM devices. This can be cumbersome when doing FPGA development in an embedded environment, and does not have an easy path to flight. Currently, FPGAs used in space applications are usually programmed via multiple space-qualified PROM devices that are physically large and require extra circuitry (typically including a separate one-time programmable FPGA) to enable them to be used for this application. This technology adds a cPCI interface device with a simple, flexible, high-performance backend interface supporting multiple backend FPGAs. It includes a mechanism for programming the FPGAs directly via the microprocessor in the embedded system, eliminating specialized hardware, software, and PROM devices and their associated circuitry. It has a direct path to flight, and no extra hardware and minimal software are required to support reprogramming in flight. The device added is currently a small FPGA, but an advantage of this technology is that the design of the device does not change, regardless of the application in which it is being used. This means that it needs to be qualified for flight only once, and is suitable for one-time programmable devices or an application specific integrated circuit (ASIC). An application programming interface (API) further reduces the development time needed to use the interface device in a system.

Clark, Duane I.↗