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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 343 records · Page 19
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Dynamic Manipulation in Piezoresponse Force Microscopy: Creating Nonequilibrium Phases with Large Electromechanical Response

We discuss how domain walls and topological defects in ferroelectric materials have emerged as a powerful tool for functional electronic devices including memory and logic. Similarly, wall interactions and dynamics underpin a broad range of mesoscale phenomena ranging from giant electromechanical responses to memory effects. Exploring the functionalities of individual domain walls, their interactions, and controlled modifications of the domain structures is crucial for applications and fundamental physical studies. However, the dynamic nature of these features severely limits studies of their local physics since application of local biases or pressures in piezoresponse force microscopy induce wall displacement as a primary response. Here, we introduce an approach for the control and modification of domain structures based on automated experimentation, whereby real-space image-based feedback is used to control the tip bias during ferroelectric switching, allowing for modification routes conditioned on domain states under the tip. This automated experiment approach is demonstrated for the exploration of domain wall dynamics and creation of metastable phases with large electromechanical response.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2024

Recent advancements in chiral spintronics: from molecular-level insights to device applications. A prospect based on the interplay between physical and chemical properties of chiral systems

This review discusses recent advancements in chiral-based spin-electronic devices achieved using suitable combinations of organic, inorganic and hybrid materials. The focus is on how chirality can be effectively used to control spin in practical applications, particularly in spintronic sensors and consumer devices. Interestingly, the underlying mechanism for this control is the chiral-induced spin selectivity (CISS) effect, which links the structural chirality of a material to its spin-selective electronic transport properties. The CISS effect arises from the observation that charge transmission in chiral systems is spin selective. Experimental evidence suggests a relationship between electron spin and the structural handedness of the material. In conclusion, this unique structure-transport relationship can be exploited to design a wide range of spintronics devices, including memory, transistors, logic gates and molecular q-bits.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2023

A superconducting nanowire binary shift register

We present a design for a superconducting nanowire binary shift register, which stores digital states in the form of circulating supercurrents in high-kinetic-inductance loops. Adjacent superconducting loops are connected with nanocryotrons, three-terminal electrothermal switches, and fed with an alternating two-phase clock to synchronously transfer the digital state between the loops. A two-loop serial-input shift register was fabricated with thin-film NbN and a bit error rate of less than 10 –4 was achieved, when operated at a maximum clock frequency of 83 MHz and in an out-of-plane magnetic field of up to 6 mT. A shift register based on this technology offers an integrated solution for low-power readout of superconducting nanowire single photon detector arrays and is capable of interfacing directly with room-temperature electronics and operating unshielded in high magnetic field environments.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2021

Second-Order Josephson Effect in Excitonic Insulators

We show that in electron-hole bilayers with excitonic orders arising from conduction and valence bands formed by atomic orbitals that have different parities, nonzero interlayer tunneling leads to a second-order Josephson effect. This means the interlayer electrical current is related to the phase of the excitonic order parameter as J = J c sin 2θ instead of J = J c sin θ and that the system has two degenerate ground states at θ = 0, π that can be switched by an interlayer voltage pulse. When generalized to a three dimensional stack of alternating electron-hole planes or a two dimensional stack of chains, the ac Josephson effect implies that electric field pulses perpendicular to the layers and chains can steer the order parameter phase between the two degenerate ground states, making these devices ultrafast memories. Here, the order parameter steering also applies to the excitonic insulator candidate Ta 2 NiSe 5 .

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2021

Impacts of Substrate Thinning on FPGA Performance and Reliability [Slides]

Substrate thinning is necessary in devices with flip-chip BGA packages to enable both radiation testing and component qualification and high-spatial resolution beam-based failure analysis methods. We investigated three factors affecting device performance: subsurface damage from the thinning process, reduced heat spreading in thin substrates, and changes in device switching speed. We conclude subsurface damage to crystalline Si caused by the thinning process is removable with sufficient SiO 2 slurry polishing. Local temperature differences increase minimally in devices thinned to 3 μm. Compressive stress in the Si increases globally after device thinning and leads to slowing of ring oscillator frequency by about 0.5% compared to full-thickness devices. Future work will include extending the results to submicron Si thickness values, which also has important benefits for failure analysis, debug, and security assessments. We also plan to extend this type of work to other FPGAs and other devices like memory and processors.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Evidence of Cooperative Effects for the Fe(phen) 2 (NCS) 2 Spin Crossover Molecular Complex in Polyaniline Plus Iron Magnetite

The spin crossover complex Fe(phen) 2 (NCS) 2 and its composite, Fe(phen) 2 (NCS) 2 , combined with the conducting polymer polyaniline (PANI) plus varying concentrations of iron magnetite (Fe 3 O 4 ) nanoparticles were studied. A cooperative effect is evident from the hysteresis width in the plot of magnetic susceptibility multiplied by temperature versus temperature (χ m T versus T) for Fe(phen) 2 (NCS) 2 with PANI plus varying concentrations of Fe 3 O 4 nanoparticles. The hysteresis width in the composites vary no more than 2 K with respect to the pristine Fe(phen) 2 (NCS) 2 spin crossover crystallites despite the fact that there exists a high degree of miscibility of the Fe(phen) 2 (NCS) 2 spin crossover complex with the PANI. The Fe 3 O 4 nanoparticles in the Fe(phen) 2 (NCS) 2 plus PANI composite tend to agglomerate at higher concentrations regardless of the spin state of Fe(phen) 2 (NCS) 2 . Of note is that the Fe 3 O 4 nanoparticles are shown to be antiferromagnetically coupled with the Fe(phen) 2 (NCS) 2 when Fe(phen) 2 (NCS) 2 is in the high spin state.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1989

SEU In An Advanced Bipolar Integrated Circuit

Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

Zoutendyk, John A.↗
NASA NTRS1991

Stacked-Gate FET's For Analog Memory Elements

Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.

Thakoor, Anilkumar P.↗
NASA NTRS1993

An ASIC memory buffer controller for a high speed disk system

The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

Hodson, Robert F.↗
NASA NTRS1997

Robotic Assisted Microsurgery - RAMS FY'97

JPL and Microdexterity Systems collaborated to develop new surgical capabilities. They developed a Robot Assisted Microsurgery (RAM) tool for surgeons to use for operating on the eye, ear, brain, and blood vessels with unprecedented dexterity. A surgeon can hold the surgical instrument with motions of 6 degrees of freedom with an accuracy of 25 microns in a 70 cu cm workspace. In 1996 a demonstration was performed to remove a microscopic particle from a simulated eyeball. In 1997, tests were performed at UCLA to compare telerobotics with mechanical operations. In 5 out of 7 tests, the RAM tool performed with a significant improvement of preciseness over mechanical operation. New design features include: (1) amplified forced feedback; (2) simultaneous slave robot instrumentation; (3) index control switch on master handle; and (4) tool control switches. Upgrades include: (1) increase in computational power; and (2) installation of hard disk memory storage device for independent operation and independent operation of forceps. In 1997 a final demonstration was performed using 2 telerobotics simultaneously in a microsurgery suture procedure to close a slit in a thin sheet of latex rubber which extended the capabilities of microsurgery procedures. After completing trials and demonstrations for the FDA the potential benefits for thousands of operations will be exposed.

Source record↗
NASA NTRS2008

Carbon Nanotube Switches for Communication and Memory Applications

Lateral CNT Switches: a) dc CNT switches were demonstrated to operate at low voltages, low powers and high speeds. b) RF simulations of switch in series configuration with metallized tube yielded good RF performance 1) Isolation simulated to be approx. 20 dB at 100 GHz. 2) Insertion loss simulated to be < 0.5 dB at 100 GHz. Vertical CNT Switches: a) Thermal CVD was used to mechanically constrain tubes in nanopockets; tubes not self-supporting. b) Demonstrated growth of vertically aligned arrays and single-few MWNTs using dc PECVD with Ni catalyst using optical lithography.

memory devices↗
NASA NTRS2019

NASA Electronic Parts and Packaging (NEPP) Program Status and Technology Investments Overview

The presentation provides an updated, high-level overview of the NEPP Program. The latest organizational chart is presented that shows the names of the Program and Assistant Program Managers. Additionally, the recent work that is on-going with the updating of several NASA NPDs, NPRs and technical standards is reviewed. Internal and external organizational interfaces are described. Finally, the current technology focus areas are described. These areas include passives, wide-band gap power devices, processor units (CPUs and GPUs), 2.5D and 3D device architectures, memories, and data analytics.

NEPAG↗
DOE OSTI2020

The organic redox transistor for neuromorphic computing

Inspired by the in-memory computing architectures of biological systems, neuromorphic computing using crossbar arrays of artificial synapses based on non-volatile memory (NVM) devices with variable conductances has emerged as a new paradigm to enable massively parallel and ultra-low power computing hardware for data centric applications. Although inference has been demonstrated successfully using crossbars based on a variety of NMV technologies, efficient learning and scaling to large arrays (>10 6 elements) remains a challenge due to the synaptic elements' non-ideal electrical characteristics which degrades ANN accuracy. A further challenge is that in the conductive state memristors draw large currents >μA resulting in significant voltage drops in the interconnect wires and increased probability of failure in scaled arrays. We suggest the organic polymer redox transistor (RT) is an alternate approach that could solve many of these challenges, enabling both inference and parallel outer product updates, as recently demonstrated by Fuller et al. An RT consists of redox-active channel and gate electrodes in contact with a liquid or solid electrolyte. lon insertion through the electrolyte controls the channel electronic conductivity, while electron transfer through an external circuit maintains overall charge neutrality. Unlike a rechargeable battery, in the RT the voltage built-up across the electrolyte is kept to a minimum (typically <100 mV) by using the same material for the gate and channel. Elimination of the voltage offset simplifies integration of the RT into programmable arrays by enabling the use of various selectors. RTs based on inorganic and organic materials have been recently demonstrated with conductance tuning occurring at potentials of just a few mV and hundreds to thousands of linearly and symmetrically programmable conductance states, enabling near ideal accuracy in neural network simulations. Introduced in the 1980's, redox transistors with metallic gate electrodes and organic channel materials, also known as organic electrochemical transistors (OECTs), have been explored for a variety of applications such as chem- and bio-sensing, neural interfaces, and low cost printed circuits. A typical channel material for OECTs is the conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonate) (PEDOT:PSS). PEDOT is a p-type semiconducting polymer with mobile positively charged polarons that hop chain-to-chain.

Talin, Albert Alec↗
DOE OSTI2020

Smart memory buffers

An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Beyond Binary: Automated PLC Memory Forensics through RGB Image Analysis and Deep Learning

The introduction of Industry 4.0 and the evolution of industrial control systems (ICS) to adopt Internet-based technologies enhanced productivity, but have inadvertently increased their vulnerability to cyber-based malicious attacks. When an ICS system is compromised, security analysts need to identify the root cause quickly to start the recovery process and develop mitigation strategies to safeguard against future instances. Memory forensics is critical in the analysis process to ascertain what occurred. To date, approaches to analyze the persistent memory in ICS devices are limited, and almost nonexistent for volatile memory. This paper proposes an automated methodology, COMA, for PLC memory dump analysis using computer vision and deep learning techniques. Specifically, COMA converts the sequences of bytes in a PLC memory dump to RGB pixels and creates a deep learning model that learns the underlying patterns and features of pre-labeled forensic artifacts in images and segments them into distinct regions. COMA then uses the trained model to automatically segment new memory images and extract forensic artifacts. We evaluate COMA on a Schneider Electric Modicon M221 PLC involving two cyber-based attack scenarios: (i) code injection and (ii) code modification. The empirical results show that COMA can successfully detect attack artifacts in memory dumps in both scenarios.

Asmar Awad, Rima↗
DOE OSTI2023

Nanostructured devices having perovskite nanocrystal layer for photodetection, optical memory, and neuromorphic functionality

The present disclosure relates to a device that includes a perovskite nanocrystal (NC) layer, a charge separating layer, an insulating layer, a gate electrode, a cathode, and an anode, where the charge separating layer is positioned between the perovskite NC layer and the insulating layer, the insulating layer is positioned between the charge separating layer and the gate electrode, and the cathode and the anode both electrically contact the charge separating layer and the insulating layer. In some embodiments of the present disclosure, the device may be configured to operate as at least one of a photodetector, an optical switching device, and/or a neuromorphic switching device.

Blackburn, Jeffrey Lee↗
DOE OSTI2023

A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write Paths

The dream of achieving a universal memory that can provide robust non-volatile memory states along with low-energy operation has been the key driving force of memory research. Despite dominating the memory market, conventional charge-based memories cannot satisfy these requirements. However, UltraRAM, an oxide-free charge-based memory cell, aims to achieve both of these requirements. This device achieves non-volatility (with an endurance of over 10 7 cycles and a retention of over 1000 years) along with switching at low-voltage (±2.3 V) utilizing a triple-barrier resonant tunneling (TBRT) structure made of InAs/AlSb. In this work, we propose an array design for UltraRAM-based memory devices. Our proposed memory array features separate read-write path and eliminates the possibility of accidentally switching the memory states stored in the array. Moreover, our design allows us to read all the cells in a column in one cycle without imposing any limit on the scalability. Besides, since the read operation in our proposed design is independent of the write mechanism, there is flexibility to optimize the read operation for memory and in-memory computing applications.

Alam, Shamiul↗
NASA NTRS1985

Bubble memory module for spacecraft application

Bubble domain technology offers an all-solid-state alternative for data storage in onboard data systems. A versatile modular bubble memory concept was developed. The key module is the bubble memory module which contains all of the storage devices and circuitry for accessing these devices. This report documents the bubble memory module design and preliminary hardware designs aimed at memory module functional demonstration with available commercial bubble devices. The system architecture provides simultaneous operation of bubble devices to attain high data rates. Banks of bubble devices are accessed by a given bubble controller to minimize controller parts. A power strobing technique is discussed which could minimize the average system power dissipation. A fast initialization method using EEPROM (electrically erasable, programmable read-only memory) devices promotes fast access. Noise and crosstalk problems and implementations to minimize these are discussed. Flight memory systems which incorporate the concepts and techniques of this work could now be developed for applications.

Hayes, P. J.↗