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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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The new test method was based on the use of a raster-scanned optical stimulus in combination with special electrical test procedures. The raster-scanned optical stimulus was provided by an optical spot scanner, an instrument that combines a scanning optical microscope with electronic instrumentation to process and display the electric photoresponse signal induced in a device that is being tested.
Tests performed to determine accuracy and efficiency of bus separators used in microprocessors are presented. Functional, AC parametric, and DC parametric tests were performed in a Tektronix S-3260 automated test system. All the devices passed the functional tests and yielded nominal values in the parametric test.
Electrical characterization tests were performed on two different manufactured types of integrated circuits. The devices were subjected to functional and AC and DC parametric tests at ambient temperatures of -55 C, -20 C, 25 C, 85 C, and 125 C. The data were analyzed and tabulated to show the effect of operating conditions on performance and to indicate parameter deviations among devices in each group. Accuracy was given precedence over test time efficiency where practical, and tests were designed to measure worst case performance.
The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described.
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The procedures described by Danchenko et al. (1980) are applied to devices of RCA's Z-process (100,000 rad-hard). A thermal annealing investigation of the Z-process reveals an annealing behavior of the p-channels that is anomalous when compared with the p-channels of the commercial and J-processes. It is noted that the thermal annealing-induced shift of the threshold potential extends far below the original value; this necessitated the development of a new mathematical treatment, the treatment presented in the paper.
A radiation hardened version of the C2L process has been developed that utilizes all-low-temperature processes subsequent to channel oxidation. This process has been used on 1K RAMS. The RAMs functioned reliably at a dose of 200,000 rads (Si) and failed at a dose of 500,000 rads (Si). The 1K RAM is capable of operating from 7.5 to 12 volts and has an access time from address change of 160 nsec at 10 volts
Annealing of radiation damage was investigated in the commercial, Z- and J-processes of the RCA CD4007A ICs in the temperature range from -140 C to +375 C. Tempering curves were analyzed for activation energies of thermal annealing, following irradiation at -140 C. It was found that at -140 C, the radiation-induced shifts in the threshold potentials were similar for all three processes. The radiation hardness of the Z- and J-process is primarily due to rapid annealing of radiation damage at room temperature. In the region -140 to 20 C, no dopant-dependent charge trapping is seen, similar to that observed at higher temperatures. In the unbiased Z-process n-channels, after 1 MeV electron irradiation, considerable negative charge remains in the gate oxide.
Circuit synchronizes clock and gate signals within one-quarter of clock cycle. Clock synchronizer with one-quarter-cycle skew constructed from three flip-flops, three NAND gates, and inverter. In addition gate signal to which clock synchronized, circuit requires square-wave input at twice desired clock frequency.
An analytical method was developed to predict the heavy-ion-induced upset rate of static random access memory (SRAM) cells. The method was applied to the design of a memory with asymmetrical cells where the goal was to increase the upset rate in order to increase the number of observed upsets in a space environment. The asymmetry is achieved by increasing the drain area of selected transistors in the cell. Results from the analytical model for a space environment indicate the upset rate for the experimental asymmetrical cell (17.2 upsets/1 kbit-year) will be 4.7 times larger than the upset rate for the minimum-geometry balanced cell (3.6 upsets/1 kbit-year). The asymmetrical SRAM was designed into a test chip intended for the Combined Release and Radiation Effects Satellite (CRRES).
New rechargeable battery technology is described and compared with classical primary battery back-up of SRAM PC cards. Thin solid polymer electrolyte cells with the thickness of TSOP memory components (1 mm nominal, 1.1 mm max) and capacities of 14 mAh/sq cm can replace coin cells. The SRAM PC cards with permanently installed rechargeable cells and optional electrochromic low battery voltage indicators will free the periodic PC card user from having to 'feed' their PC cards with coin cells and will allow a quick visual check of stored cards for their battery voltage status.
This paper presents a programmable architecture for sequential pass transistor circuits. The resulting circuits are such that a state machine with N states and M output is constructed using a single layout replicated N + M times.
A constant current source has been designed which makes use of on chip electrically erasable memory to adjust the magnitude and temperature coefficient of the output current. The current source includes a voltage reference based on the difference between enhancement and depletion transistor threshold voltages. Accuracy is +/- 3% over the full range of power supply, process variations, and temperature using eight bits for tuning.
This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.
The performance of minimal stuck-at fault test sets at detecting bridging faults are evaluated. New functional models of circuit primitives are presented which allow accurate representation of bridging faults under switch-level simulation. The effectiveness of the patterns is evaluated using both voltage and current testing.
In testing sequential circuits, internal faults in the storage elements (SE's) are sometimes modeled as stuck-at faults in the combinational circuits surrounding the SE. The detection of some transistor-level faults that cannot be modeled as stuck-at are considered. These feed-through faults cause the cell to become either data-feed-through, which makes the cell combinational, or clock-feed-through, which causes the clock signal or its complement to appear at the output. Under such faults, the cell does not function as a memory element. Here it is shown that such faults may or may not be detected depending on delays involved. Conditions under which race-ahead occurs are identified.
The occurrence of multiple upset errors during ground tests can contaminate the data and lead to error cross sections which are too high. In space, multiple errors may produce higher upsets than predicted and if they occur in single words they can defeat error detection and correction hardware. This investigation involves data which were taken during an experimental study of dose imprint effects in static memories. The results show that multiple errors occurred mainly for heavy ions with high linear energy transfers and with the majority of these in the soft upset sections of the dose-imprinted memory samples. The percentages of the total number of errors which were singles, doubles, and triplets, were determined as a function of LET, dose, and soft or hard section of the devices. The experimental observations are compared to the predictions of simple binomial statistics.
The subject orifice pulse tube cooler employs dual opposed compressor pistons, clearance seals, moving coil linear motors, and flexible bearings cooling capacity is 100 watts at 200 K. A matrix of optimizations explored load temperatures and cooling capacities of 50 K, 100 K, 200 K, 1 watt, 10 watts, and 100 watts. The optimization process resulted in a design with zero second entrance flow and a non-resonant pulse tube. Topics include performance results, mechanical design, and development problems and solutions. The development seeks to use orifice pulse tube mechanical simplicity to achieve a computer cooler with acceptable efficiency, low materials cost, low labor cost, long life, high reliability, low vibration, operation at the standard 60 Hz U.S. grid frequency, and control through simple drive and control electronics.