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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Apparatus and methods are provided for packaging IC chips together with integrated antenna modules designed to provide a closed EM (electromagnetic) environment for antenna radiators, thereby allowing antennas to be designed independent from the packaging technology.
Tantalum films incorporated into superconducting circuits have exhibited low surface losses, resulting in long-lived qubit states. The remaining loss pathways originate in microscopic defects that manifest as two level systems (TLSs) at low temperatures. These defects limit performance, so careful attention to tantalum film structures is critical for optimal use in quantum devices. In this work, we investigate the growth of tantalum using magnetron sputtering on sapphire, Si, and photoresist substrates. In the case of sapphire, we present procedures for the growth of fully-oriented films with α-Ta [1 1 1]//Al2O3 [0 0 0 1] and α-Ta [1 −1 0]//Al2O3 [1 0 −1 0] orientational relationships and having residual resistivity ratio (RRR) ∼ 60 for 220 nm thick films. On Si, we find a complex grain texturing with Ta [1 1 0] normal to the substrate and RRR ∼ 30. We further demonstrate airbridge fabrication using Nb to nucleate α-Ta on photoresist surfaces. For the films on sapphire, resonators show TLS-limited quality factors of 1.3 ± 0.3 × 106 at 10 mK (for a waveguide gap and conductor width of 3 and 6 μm, respectively). Structural characterization using scanning electron microscopy, x-ray diffraction, low temperature transport, secondary ion mass spectrometry, and transmission electron microscopy reveal the dependence of residual impurities and screw dislocation density on processing conditions. The results provide practical insights into the fabrication of advanced superconducting devices including qubit arrays and guide future works on crystallographically deterministic qubit fabrication.
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Qualification testing and failure analysis of integrated microcircuits
A receiver belonging to the family of integrated planar receivers has been developed at 90 GHz. It consists of a planar Schottky-diode placed at the feed of a dipole-probe suspended inside an integrated horn antenna. The measured planar mixer single-sideband conversion loss at 91.2 GHz (LO) with a 200 MHz IF frequency is 8.3dB plus or minus 0.3dB. The low cost of fabrication and simplicity of this design makes it ideal for millimeter and submillimeter-wave receivers.
A circuit model for an existing silicon integrated bipolar junction transistor (IBJT) is used to evaluate presently achievable high frequency circuit performance. The relationship between circuit model and processing parameters are semi-quantitatively explored to make predictions on the frequency response, which can be achieved through realistic device fabrication modifications. A new figure of merit is introduced, which is defined as the signal frequency at which an integrated bipolar junction transistor can deliver a power gain of G. The most sensitive parameter influencing attainable high frequency IBJT performance is base resistance.
A technique is developed for directly integrating infrared photoconductive PbS detector material with MOS transistors. A layer of chromium, instead of aluminum, is deposited followed by a gold deposition in order to ensure device survival during the chemical deposition of the PbS. Among other devices, a structure was fabricated and evaluated in which the PbS was directly coupled to the gate of a PMOS. The external bias, load, and source resistors were connected and the circuit was operated as a source-follower amplifier. Radiometric evaluations were performed on a variety of different MOSFETs of different geometry. In addition, various detector elements were simultaneously fabricated to demonstrate small element capability, and it was shown that elements of 25 x 25 microns could easily be fabricated. Results of room temperature evaluations using a filtered 700 K black body source yielded a detectivity at peak wavelength of 10 to the 11th cm (root Hz)/W at 100 Hz chopping frequency.
A technique is described for determining the applicability of a particular process for the fabrication of large-scale integrated (LSI) circuits. Test arrays were developed to isolate various critical processing steps in a fabrication sequence and a statistical evaluation of these steps was carried out that related yield or success in achieving a desired result to the number of times the results were attempted. It was found that, in general, yield is a sensitive function of physical dimensions as is the packing density of a particular array. It is, therefore, possible to generate an optimum set of physical dimensions or design rules that maximize the expected number of working circuits on a wafer.
Depletion-mode load devices can be integrated with DMOS transistors without any extra diffusions or ion implantation processing steps by judicious choice of the substrate crystal orientation and resistivity. For low voltage operation line-type 1, 1, 1 crystal orientation should be used. The line-type 1, 1, 1 crystal orientation also yields a higher transconductance for the DMOS transistor than the line-type 1, 0, 0 orientation. The geometry of the load device and the DMOS transistor can be made ratioless to conserve area. Self-aligned gates, hitherto considered incompatible with DMOS transistors, have been incorporated in the structure. The experimental DMOS inverters, using a conservative design, have achieved 4-ns propagation delay, 1.3-V operation, and 2-pJ propagation delay-power dissipation product.
Damage mechanism in semiconductors from space radiation and effects on various microcircuits
Postmortem flaw detection methods and equipment for IC failure analysis
Automatic high speed IC test equipment and procedure
Program results are described in which the use of a/high permittivity rectangular dielectric image waveguide has been investigated for use in microwave and millimeter wavelength circuits. Launchers from rectangular metal waveguide to image waveguide are described. Theoretical and experimental evaluations of the radiation from curved image waveguides are given. Measurements of attenuation due to conductor and dielectric losses, adhesives, and gaps between the dielectric waveguide and the image plane are included. Various passive components are described and evaluations given. Investigations of various techniques for fabrication of image waveguide circuits using ceramic waveguides are also presented. Program results support the evaluation of the image line approach as an advantageous method for realizing low loss integrated electronic circuits for X-band and above.
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Next generation space-based robotics systems will be constructed using distributed architectures where electronics capable of working in the extreme environments of the planets of the solar system are integrated with the sensors and actuators in plug-and-play modules and are connected through common multiple redundant data and power buses.
This work compares design layouts and circuit simulations of the next two prototype NASA Glenn SiC JFET-R IC fabrication runs designated “IC Gen. 12” and “IC Gen. 13”. Even though both generations employ the same physical JFET gate length and chip size, SPICE simulations predict drastic improvements to IC capabilities and performance metrics for Gen. 13 over Gen. 12. The main factors behind simulated performance differences are thinner n-channel layer leading to reduced operating voltages and switch to stepper-based photolithography that enables roughly 4-fold layout area reductions for functionally identical circuit blocks.
New effects that complicate the application of linear devices in space are discussed, including enhanced damage at low dose rate and proton damage, which cause permanent degradtion.
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