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At least 307 records · Page 17

A review of crosstalk polymorphic circuits and their scalability

Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.

97 MATHEMATICS AND COMPUTING↗

Simulating plasma wave propagation on a superconducting quantum chip

Quantum computers may one day enable the efficient simulation of strongly coupled plasmas that lie beyond the reach of classical computation in regimes where quantum effects are important and the scale separation is large. Here, in this article, we take a first step toward efficient simulation of quantum plasmas by demonstrating linear plasma wave propagation on a superconducting quantum chip. Using high-fidelity and highly expressive device-native gates, combined with an error-mitigation technique, we simulate the scattering of laser pulses from inhomogeneous plasmas. Our approach is made feasible by the identification of a suitable local spin model whose excitations mimic plasma waves, and whose circuit implementation requires a lower gate count than other proposed approaches that would require a future fault-tolerant quantum computer. This work opens avenues to study more complicated phenomena that cannot be simulated efficiently on classical computers, such as nonlinear quantum dynamics when strongly coupled plasmas are driven out of equilibrium.

general physics↗

Control and protection system for paralleled modular static inverter-converter systems

A control and protection system was developed for use with a paralleled 2.5-kWe-per-module static inverter-converter system. The control and protection system senses internal and external fault parameters such as voltage, frequency, current, and paralleling current unbalance. A logic system controls contactors to isolate defective power conditioners or loads. The system sequences contactor operation to automatically control parallel operation, startup, and fault isolation. Transient overload protection and fault checking sequences are included. The operation and performance of a control and protection system, with detailed circuit descriptions, are presented.

Birchenough, A. G.↗

Photovoltaic module and array reliability

Several statistical reliability studies have been conducted in areas of photovoltaic component design covering cell failure, interconnect fatigue, glass breakage and electrical insulation breakdown. This paper integrates the results from these various studies and draws general conclusions relative to optimal reliability features for future modules. The described analysis is based on designing for specified low levels of component failures and then controlling the degrading effects of the failures through the use of fault tolerant circuitry and module replacement. Means of selecting the cost-optimal level of component failures, circuit redundancy, and module replacement are described.

Ross, R. G., Jr.↗

Source-circuit design overview

The source circuit is the fundamental electrical building block of a large central-station array; it consists of a series-parallel network of solar cells that develops full system voltage. The array field is generally made up of a large number of parallel source circuits. Source-circuit electrical configuration is driven by a number of design considerations, which must be considered simultaneously. Array fault tolerance and hot spot heating endurance are examined in detail.

Ross, R. G., Jr.↗

Test chips and ASIC qualification

A test chip set being developed to aid in the qualification of spaceborne Application Specific Integrated Circuits (ASICs) is described. The chip set consists of a process monitor for process parameter verification, a fault chip for yield analysis, a reliability chip for ASIC failure rate analysis, and total ionizing dose and single event upset chips for radiation effect analysis. The test structures contained in these chips are discussed along with representative test results.

Buehler, M. G.↗

Compact, Reliable EEPROM Controller

A compact, reliable controller for an electrically erasable, programmable read-only memory (EEPROM) has been developed specifically for a space-flight application. The design may be adaptable to other applications in which there are requirements for reliability in general and, in particular, for prevention of inadvertent writing of data in EEPROM cells. Inadvertent writes pose risks of loss of reliability in the original space-flight application and could pose such risks in other applications. Prior EEPROM controllers are large and complex and do not provide all reasonable protections (in many cases, few or no protections) against inadvertent writes. In contrast, the present controller provides several layers of protection against inadvertent writes. The controller also incorporates a write-time monitor, enabling determination of trends in the performance of an EEPROM through all phases of testing. The controller has been designed as an integral subsystem of a system that includes not only the controller and the controlled EEPROM aboard a spacecraft but also computers in a ground control station, relatively simple onboard support circuitry, and an onboard communication subsystem that utilizes the MIL-STD-1553B protocol. (MIL-STD-1553B is a military standard that encompasses a method of communication and electrical-interface requirements for digital electronic subsystems connected to a data bus. MIL-STD- 1553B is commonly used in defense and space applications.) The intent was to both maximize reliability while minimizing the size and complexity of onboard circuitry. In operation, control of the EEPROM is effected via the ground computers, the MIL-STD-1553B communication subsystem, and the onboard support circuitry, all of which, in combination, provide the multiple layers of protection against inadvertent writes. There is no controller software, unlike in many prior EEPROM controllers; software can be a major contributor to unreliability, particularly in fault situations such as the loss of power or brownouts. Protection is also provided by a powermonitoring circuit.

Katz, Richard↗

Mid-circuit correction of correlated phase errors using an array of spectator qubits

Scaling up invariably error-prone quantum processors is a formidable challenge. Although quantum error correction ultimately promises fault-tolerant operation, the required qubit overhead and error thresholds are daunting. In a complementary proposal, colocated, auxiliary “spectator” qubits act as in situ probes of noise and enable real-time, coherent corrections of data qubit errors. We used an array of cesium spectator qubits to correct correlated phase errors on an array of rubidium data qubits. By combining in-sequence readout, data processing, and feedforward operations, these correlated errors were suppressed within the execution of the quantum circuit. The protocol is broadly applicable to quantum information platforms and establishes key tools for scaling neutral-atom quantum processors: mid-circuit readout of atom arrays, real-time processing and feedforward, and coherent mid-circuit reloading of atomic qubits.

Science & Technology - Other Topics↗

Advanced Sensor Deployment for Distribution System State Estimation and Fault Identification: Preprint

Distribution systems are currently facing steep operational challenges as a result of the rapidly increasing integration of renewables and other distributed energy resources (DERs)at both the primary and secondary circuit levels. Distribution utilities and system operators have traditionally had some visibility of their primary circuits using low-frequency supervisory control and data acquisition systems, and they have had very poor if not zero visibility of the secondary circuits where the presence of DERs is constantly increasing. Therefore, this paper presents simulation studies to demonstrate the benefits of an advanced, high-fidelity sensor technology, called as the Meta-Alert System (MAS), developed by Electrical Grid Monitoring Ltd. (EGM), on the distribution grid. First, a reliable model of the EGM sensors is developed, and then two use cases - distribution system state estimation (DSSE) and fault identification - are simulated to evaluate the performance of the MAS technology. Simulation results on the Electric Power Research Institute J1feeder demonstrate that the MAS can effectively participate in system-level DSSE programs and can detect and locate faults faster than traditional distribution protection schemes.

distribution system monitoring↗

A quantum algorithm for string matching

Algorithms that search for a pattern within a larger data-set appear ubiquitously in text and image processing. Here, we present an explicit, circuit-level implementation of a quantum pattern-matching algorithm that matches a search string (pattern) of length M inside a longer text of length N. Our algorithm has a time complexity of $\tildeO$($\sqrt{N}$), while the space complexity remains modest at O(N+ M). We report the quantum gate counts relevant for both pre-fault-tolerant and fault-tolerant regimes.

Physics↗

A Step Response Based Mixed-Signal BIST Approach for Continuous-time Linear Circuits

A new Mixed-Signal Built-in self-test approach that is based upon the step response of a reconfigurable (or multifunction) analog block is presented in this paper. The technique requires the overlapping step response of the Circuit Under Test (CUT) for two circuit configurations. Each configuration can be realized by changing the topology of the CUT or by sampling two CUT nodes with differing step responses. The technique can effectively detect both soft and hard faults and does not require an analog-to-digital converter (ADC) and/or digital-to-analog converter(DAC). It also does not require any precision voltage sources or comparators. This approach does not require any additional analog circuits to realize the test signal generator and sample circuits. The paper is concluded with the application of the proposed approach to a circuit found in the work of Epstein et al and two ITC 97 analog benchmark circuits.

Walker, Alvernon↗

A Step Response Based Mixed-Signal BIST Approach

A new Mixed-Signal Built-in Self-test approach that is based upon the step response of a reconfigurable (or multifunction) analog block is presented in this paper. The technique requires the overlapping step response of the Circuit Under Test (CUT) for two circuit configurations. Each configuration can be realized by changing the topology of the CUT or by sampling two CUT nodes with differing step responses. The technique can effectively detect both soft and hard faults and does not require an analog-to-digital converter (ADC) and/or digital-to-analog converter( DAC). It also does not require any precision voltage sources or comparators. The approach does not require any additional analog circuits to realize the test signal generator and a two input analog multiplexer for CUT test node sampling. The paper is concluded with the application of the proposed approach to a circuit found in the work of Epstein et a1 and two ITC 97 analog benchmark circuits.

Walker, Alvernon↗

Scalable Circuit Cutting and Scheduling in a Resource-constrained and Distributed Quantum System

Despite quantum computing's rapid development, current systems remain limited in practical applications due to their limited qubit count and quality. Various technologies, such as superconducting, trapped ions, and neutral atom quantum computing technologies are progressing towards a fault tolerant era, however they all face a diverse set of challenges in scalability and control. Recent efforts have focused on multi-node quantum systems that connect multiple smaller quantum devices to execute larger circuits. Future demonstrations hope to use quantum channels to couple systems, however current demonstrations can leverage classical communication with circuit cutting techniques. This involves cutting large circuits into smaller subcircuits and reconstructing them post-execution. However, existing cutting methods are hindered by lengthy search times as the number of qubits and gates increases. Additionally, they often fail to effectively utilize the resources of various worker configurations in a multi-node system. To address these challenges, we introduce FitCut, a novel approach that transforms quantum circuits into weighted graphs and utilizes a community-based, bottom-up approach to cut circuits according to resource constraints, e.g., qubit counts, on each worker. FitCut also includes a scheduling algorithm that optimizes resource utilization across workers. Implemented with Qiskit and evaluated extensively, FitCut significantly outperforms the Qiskit Circuit Knitting Toolbox, reducing time costs by factors ranging from 3 to 2000 and improving resource utilization rates by up to 3.88 times on the worker side, achieving a system-wide improvement of 2.86 times.

Kan, Shuwen [Fordham University]↗

Life support subsystem monitoring instrumentation

The recognition of the need for instrumentation in manned spacecraft life-support subsystems has increased significantly over the past several years. Of the required control and monitoring instrumentation, this paper will focus on the monitoring instrumentation as applied to life-support subsystems. The initial approach used independent sensors, independent sensor signal conditioning circuitry, and independent logic circuitry to provide shutdown protection only. This monitoring system was replaced with a coordinated series of printed circuit cards, each of which contains all the electronics to service one sensor and provide performance trend information, fault detection and isolation information, and shutdown protection. Finally, a review of sensor and instrumentation problems is presented, and the requirement for sensors with built-in signal conditioning and provisions for in situ calibration is discussed.

Powell, J. D.↗

High-Frequency Signature-Based Fault Detection for Future MV Distribution Grids: Preprint

Increased deployment of Distributed Energy Resources (DERs) and microgrids are significantly changing the operation of distribution grid. Increasing penetration of power electronics based DERs also raise several operational problems such as protection coordination issues, voltage raise, recloser synchronization, stability, and frequency control. Legacy systems are designed for unidirectional power flow. Bidirectional power flows, and varying short circuit levels are some of the major challenges in implementing these legacy protection schemes for future power grid with high penetration of power electronics based DERs. Inverter based DER’s can contribute to a maximum of 2 p.u. fault current. Interconnection standards might require even lower fault current contribution. If these protection related challenges are not addressed, it will result in limiting the penetration of DERs in distribution feeders. In this paper, the feasibility of high frequency signature generated by transients is evaluated to identify and locate faults in a distribution system. The paper will discuss the need for an accurate line modeling approach to accurately capture the high frequency signatures. These high frequency signatures are naturally occurring electromagnetic transients for events such as switching events in the network, faults events, etc. This is different than that implemented in transmission systems as the proposed approach utilizes advanced signal processing techniques to retrieve valuable information from the high frequency signatures generated during faults and does not just rely on time delay measurements between reflections of the high frequency signals. In the full paper, information of a modified IEEE distribution feeder test system to accurately model the high frequency signatures will be provided. The distribution lines will be modeled using universal line modeling (ULM) technique in an electromagnetic transients program (EMTP) modeling platform. Different test cases will be simulated and these test cases will include different fault types, multiple fault locations, capacitor bank switching, etc. The feeder system modeled for these simulations will also include power electronics based DERs. Additionally, experimental results demonstrating the high frequency signatures generated due to a transient event in a medium voltage (13.8 kV) distribution line will also be presented in the full paper. Furthermore, the analysis combined with simulation and experimental results in the full paper will help demonstrate the feasibility and efficacy of the proposed protection scheme. The developed protection scheme will not just help solve problems generated by bidirectional current flow, varying short-circuit current capacity, but also help in proliferation of DERs in distribution systems.

41 EE - Solar Energy Technologies Office (EE-4S)↗

Adaptive Fault Current-Limiting Control of MMC for Protection of Multiterminal HVDC Systems

A crucial requirement of the protection system for multi-terminal high-voltage DC (MTDC) transmission is that it is capable of selectively isolating the faulty area from the healthy part of the network using DC circuit breakers (DCCBs), while ensuring continuous operation of converter stations in the healthy part of the network. But in the half-bridge modular multilevel converters (HB-MMCs) based MTDC system, since HB-MMCs do not have fault current absorption capability, when a DC fault occurs, the rising fault currents can quickly reach the blocking threshold within a few milliseconds and disrupt the operation of the MMCs in the healthy part. To facilitate fault-ride-through capability of MTDC system, large DC reactors are often considered in series with DCCBs to reduce the rate of rise of the fault current and prevent blocking the MMCs in the healthy part of the DC networks; however, large DC reactors prohibitively increase the cost of the system, introduce stability issues and can create post-fault oscillations. This paper presents an adaptive fault current-limiting control method for MMCs to avoid their blocking and enable the continuous operation of the healthy part of MTDC systems. The method contains two parts: The first part is based on circulating current feedforward control, which emulates virtual reactors in each arm of an MMC, and is immediately activated when the fault current starts to increase to reduce the rate of rise of the fault current. The second part temporarily bypasses all the submodules when the fault current exceeds a preset threshold, complementing the fault current-limiting effect of the first part. Neither part requires fault detection signals, and they are automatically activated during faults. Simulation case studies of a four-terminal bipolar MMC-based high-voltage DC system are presented to demonstrate the effectiveness of the proposed control methods.

active fault current limiting↗

Accelerated Aging with Electrical Overstress and Prognostics for Power MOSFETs

Power electronics play an increasingly important role in energy applications as part of their power converter circuits. Understanding the behavior of these devices, especially their failure modes as they age with nominal usage or sudden fault development is critical in ensuring efficiency. In this paper, a prognostics based health management of power MOSFETs undergoing accelerated aging through electrical overstress at the gate area is presented. Details of the accelerated aging methodology, modeling of the degradation process of the device and prognostics algorithm for prediction of the future state of health of the device are presented. Experiments with multiple devices demonstrate the performance of the model and the prognostics algorithm as well as the scope of application. Index Terms Power MOSFET, accelerated aging, prognostics

Saha, Sankalita↗

TQEA: Temporal Quantum Error Analysis

For the last few years quantum computers have captured researchers’ interest in solving complicated problems in finance, chemistry, machine learning, and many other NP problems. Quantum computing benefits from parallel computation, entanglement, and calculation speedup compared to classical computing. Even though the operations and number of qubits in quantum computers are limited, previous research showed that using quantum computers can be beneficial. These benefits gained researchers’ interest to work on the improvement of quantum computers and overcome the limitations by building more advanced quantum computers with fault tolerance capability, more physical qubits, and better operational gates. In practice, Quantum applications would be translated into Quantum Circuits and each circuit can contain one or many entanglements (s), single qubits operations, and readouts. The importance of running Quantum applications with controlled errors or without errors is critical to the desired result from Quantum readout. In this paper, we study the characteristics of superconducting quantum machines along with the previously proposed methods of Quantum error detection/correction and in order to build a better error model we propose a temporal method for analyzing the the behavior of qubits errors (T1 and T2), frequency of operation, entanglement errors, and readout errors. In order to detect and predict the behavior of each machine, we use simple exponential smoothing analysis on heuristic calibration data. Finally, based on observation, we show that based on frequency, qubits, readout and single operation errors we can build a temporal based model to study and predict the outcome of runs on each Quantum machine.

Baheri, Betis↗