Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “PROCESSOR”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 307 records · Page 17
All sourcesNASA NTRSDOE OSTI
NASA NTRS1982

Seasat synthetic-aperture radar data reduction using parallel programmable array processors

This paper presents a digital processing system that produces the Seasat synthetic-aperture radar (SAR) imagery. The system consists of a SEL 32/77 host minicomputer and three AP-120B array processors. The partitioning of the SAR processing functions and the design of software modules is described. The rationale for selecting the parallel array processor architecture and the methodology for developing the parallel processing scheme on this system is described. This system attains a Seasat SAR data reduction speed of 2.5 h per 25-m resolution 4-look and 100 km x 100 km image frame. A preliminary performance evaluation of this parallel processing system and potential future applications for remote sensing data reduction are described.

Wu, C.↗
NASA NTRS1982

Real-time optical synthetic aperture radar /SAR/ processor

A description is given of a real-time optical synthetic aperture radar (SAR). The processor employs an acoustooptic device as the input electronic-to-optical transducer and a CCD camera that serves as the optical detector and simultaneously performs the focusing of the SAR image in the azimuth direction. The performance criteria of the optical processor that are discussed include azimuth resolution, image size in azimuth, range resolution, image size in range, flexibility, and dynamic range.

Psaltis, D.↗
NASA NTRS1982

A microprocessor-based one dimensional optical data processor for spatial frequency analysis

A high degree of accuracy was obtained in measuring the spatial frequency spectrum of known samples using an optical data processor based on a microprocessor, which reliably collected intensity versus angle data. Stray light control, system alignment, and angle measurement problems were addressed and solved. The capabilities of the instrument were extended by the addition of appropriate optics to allow the use of different wavelengths of laser radiation and by increasing the travel limits of the rotating arm to + or - 160 degrees. The acquisition, storage, and plotting of data by the computer permits the researcher a free hand in data manipulation such as subtracting background scattering from a diffraction pattern. Tests conducted to verify the operation of the processor using a 25 mm diameter pinhole, a 39.37 line pairs per mm series of multiple slits, and a microscope slide coated with 1.091 mm diameter polystyrene latex spheres are described.

Collier, R. L.↗
NASA NTRS1983

The development of a power spectral density processor for C and L band airborne radar scatterometer sensor systems

A real-time signal processor was developed for the NASA/JSC L-and C-band airborne radar scatterometer sensor systems. The purpose of the effort was to reduce ground data processing costs. Conversion of two quadrature channels of data (like and cross polarized) was made to obtain Power Spectral Density (PSD) values. A chirp-z transform (CZT) approach was used to filter the Doppler return signal and improved high frequency and angular resolution was realized. The processors have been tested with record signals and excellent results were obtained. CZT filtering can be readily applied to scatterometers operating at other wavelengths by altering the sample frequency. The design of the hardware and software and the results of the performance tests are described in detail.

Harrison, D. A., III↗
NASA NTRS1983

SPP: A data base processor data communications protocol

The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

Fishwick, P. A.↗
NASA NTRS1982

Multibeam single frequency synthetic aperture radar processor for imaging separate range swaths

A single-frequency multibeam synthetic aperture radar for large swath imaging is disclosed. Each beam illuminates a separate ""footprint'' (i.e., range and azimuth interval). The distinct azimuth intervals for the separate beams produce a distinct Doppler frequency spectrum for each beam. After range correlation of raw data, an optical processor develops image data for the different beams by spatially separating the beams to place each beam of different Doppler frequency spectrum in a different location in the frequency plane as well as the imaging plane of the optical processor. Selection of a beam for imaging may be made in the frequency plane by adjusting the position of an aperture, or in the image plane by adjusting the position of a slit. The raw data may also be processed in digital form in an analogous manner.

Jain, A.↗
NASA NTRS1983

Parallel processing in a host plus multiple array processor system for radar

Host plus multiple array processor architecture is demonstrated to yield a modular, fast, and cost-effective system for radar processing. Software methodology for programming such a system is developed. Parallel processing with pipelined data flow among the host, array processors, and discs is implemented. Theoretical analysis of performance is made and experimentally verified. The broad class of problems to which the architecture and methodology can be applied is indicated.

Barkan, B. Z.↗
NASA NTRS1983

Frequency-multiplexed and pipelined iterative optical systolic array processors

Optical matrix processors using acoustooptic transducers are described, with emphasis on new systolic array architectures using frequency multiplexing in addition to space and time multiplexing. A Kalman filtering application is considered in a case study from which the operations required on such a system can be defined. This also serves as a new and powerful application for iterative optical processors. The importance of pipelining the data flow and the ordering of the operations performed in a specific application of such a system are also noted. Several examples of how to effectively achieve this are included. A new technique for handling bipolar data on such architectures is also described.

Casasent, D.↗
NASA NTRS1983

Optical systolic array processor using residue arithmetic

The use of residue arithmetic to increase the accuracy and reduce the dynamic range requirements of optical matrix-vector processors is evaluated. It is determined that matrix-vector operations and iterative algorithms can be performed totally in residue notation. A new parallel residue quantizer circuit is developed which significantly improves the performance of the systolic array feedback processor. Results are presented of a computer simulation of this system used to solve a set of three simultaneous equations.

Jackson, J.↗
NASA NTRS1984

Investigation of TM Band-to-band Registration Using the JSC Registration Processor

The JSC registration processor performs scene-to-scene (or band-to-band) correlation based on edge images. The edge images are derived from a percentage of the edge pixels calculated from the raw scene data, excluding clouds and other extraneous data in the scene. Correlations are performed on patches (blocks) of the edge images, and the correlation peak location in each patch is estimated iteratively to fractional pixel location accuracy. Peak offset locations from all patches over the scene are then considered together, and a variety of tests are made to weed out outliers and other inconsistencies before a distortion model is assumed. Thus, the correlation peak offset locations in each patch indicate quantitatively how well the two TM bands register to each other over that patch of scene data. The average of these offsets indicate the overall accuracies of the band-to-band registration. The registration processor was also used to register one acquisition to another acquisition of multitemporal TM data acquired over the same ground track. Band 4 images from both acquisitions were correlated and an rms error of a fraction of a pixel was routinely obtained.

Yao, S. S.↗
NASA NTRS1982

A programmable power processor for high power space applications

A Programmable Power Processor (P3) has been developed for application in future large space power systems. The P3 is capable of operation over a wide range of input voltage (26 to 375 Vdc) and output voltage (24 to 180 Vdc). The peak output power capability is 18 kW (180 V at 100 A). The output characteristics of the P3 can be programmed to any voltage and/or current level within the limits of the processor and may be controlled as a function of internal or external parameters. Seven breadboard P3s and one 'flight-type' engineering model P3 have been built and tested both individually and in electrical power systems. The programmable feature allows the P3 to be used in a variety of applications by changing the output characteristics. Test results, including efficiency at various input/output combinations, transient response, and output impedance, are presented.

Lanier, J. R., Jr.↗
NASA NTRS1982

30/20 GHz communications systems baseband processor development

The architecture and system design concepts for a commercial satellite communications system planned for the 1990's has been developed. The system provides data communications between the individual users via trunking and customer premise service terminals utilizing a central switching satellite operating in a time-division multiple-access mode. Baseband processing is employed to route and control traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband processor design are being verified in the baseband processor proof-of-concept model described herein.

Brown, L.↗
NASA NTRS1984

Modeling algorithm execution time on processor arrays

An approach to modelling the execution time of algorithms on parallel arrays is presented. This time is expressed as a function of the number of processors and system parameters. The resulting model has been applied to a parallel implementation of the conjugate-gradient algorithm on NASA's FEM. Results of experiments performed to compare the model predictions against actual behavior show that the floating-point arithmetic, communication, and synchronization components of the parallel algorithm execution time were correctly modelled. The results also show that the overhead caused by the interaction of the system software and the actual parallel hardware must be reflected in the model parameters. The model has been used to predict the performance of the conjugate gradient algorithm on a given problem as the number of processors and machine characteristics varied.

Adams, L. M.↗
NASA NTRS1985

Investigation of TM Band-to-band Registration Using the JSC Registration Processor

When the Thematic Mapper (TM) imagery was first received and displayed in the fall of 1982, its radiometric lucidity and geometric fidelity was judged far superior to the multispectral scanner (MSS) imagery. The MSS data from the LANDSAT series of satellites have served well as the mainstay of satellite imagery for the remote sensing community up to now. Therefore, there is great anticipation as to the utility of this new IM imagery to advance the field of remote sensing. The thematic mapper (TM) band to band registration accuracy evaluation was discussed. In particular, the band to band registration accuracies of the TM data in the subpixel region were evaluated using the Johnson Space Center (JSC) registration processor which is ideally suited for this task. The JSC registration processor was also used to register one acquisition to another acquisition of multitemporal TM data acquired over the same ground track. The approach and the rationale behind the task, the description of the data set, the evaluation results, and the preliminary conclusions are discussed.

Yao, S. S.↗
NASA NTRS1985

Filter induced errors in laser anemometer measurements using counter processors

Simulations of laser Doppler anemometer (LDA) systems have focused primarily on noise studies or biasing errors. Another possible source of error is the choice of filter types and filter cutoff frequencies. Before it is applied to the counter portion of the signal processor, a Doppler burst is filtered to remove the pedestal and to reduce noise in the frequency bands outside the region in which the signal occurs. Filtering, however, introduces errors into the measurement of the frequency of the input signal which leads to inaccurate results. Errors caused by signal filtering in an LDA counter-processor data acquisition system are evaluated and filters for a specific application which will reduce these errors are chosen.

Oberle, L. G.↗
NASA NTRS1983

Satellite baseband processor test performance summary

A satellite baseband processor (BBP) has been developed for the NASA Lewis 30/20 GHz Satellite Communications Program. The BBP design, reported elsewhere, has been implemented in a proof-of-concept (POC) model. The results of the laboratory system tests of the POC are summarized. Bit error rate test results are presented for the FDM/TDMA communication system operating at 27.5, 110, and 550 Mbps over a variety of operating conditions. The results clearly demonstrate the applicability of baseband processing to future high capacity satellite communication system concepts. A brief description of the system concept, its function, and the role of the baseband processor are presented. The test conditions and means of simulation are also described. The methods of test evaluation and their significance in a system context are given.

Shaneyfelt, J. T.↗
NASA NTRS1985

Parallel processor programs in the Federal Government

In 1982, a report dealing with the nation's research needs in high-speed computing called for increased access to supercomputing resources for the research community, research in computational mathematics, and increased research in the technology base needed for the next generation of supercomputers. Since that time a number of programs addressing future generations of computers, particularly parallel processors, have been started by U.S. government agencies. The present paper provides a description of the largest government programs in parallel processing. Established in fiscal year 1985 by the Institute for Defense Analyses for the National Security Agency, the Supercomputing Research Center will pursue research to advance the state of the art in supercomputing. Attention is also given to the DOE applied mathematical sciences research program, the NYU Ultracomputer project, the DARPA multiprocessor system architectures program, NSF research on multiprocessor systems, ONR activities in parallel computing, and NASA parallel processor projects.

Schneck, P. B.↗