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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 307 records · Page 17

HamLib: A library of Hamiltonians for benchmarking quantum algorithms and hardware

In order to characterize and benchmark computational hardware, software, and algorithms, it is essential to have many problem instances on-hand. This is no less true for quantum computation, where a large collection of real-world problem instances would allow for benchmarking studies that in turn help to improve both algorithms and hardware designs. To this end, here we present a large dataset of qubit-based quantum Hamiltonians. The dataset, called HamLib (for Hamiltonian Library), is freely available online and contains problem sizes ranging from 2 to 1000 qubits. HamLib includes problem instances of the Heisenberg model, Fermi-Hubbard model, Bose-Hubbard model, molecular electronic structure, molecular vibrational structure, MaxCut, Max- k -SAT, Max- k -Cut, QMaxCut, and the traveling salesperson problem. The goals of this effort are (a) to save researchers time by eliminating the need to prepare problem instances and map them to qubit representations, (b) to allow for more thorough tests of new algorithms and hardware, and (c) to allow for reproducibility and standardization across research studies.

97 MATHEMATICS AND COMPUTING↗

Cybersecurity Considerations for Grid-Connected Batteries with Hardware Demonstrations

The share of renewable and distributed energy resources (DERs), like wind turbines, solar photovoltaics and grid-connected batteries, interconnected to the electric grid is rapidly increasing due to reduced costs, rising efficiency, and regulatory requirements aimed at incentivizing a lower-carbon electricity system. These distributed energy resources differ from traditional generation in many ways including the use of many smaller devices connected primarily (but not exclusively) to the distribution network, rather than few larger devices connected to the transmission network. DERs being installed today often include modern communication hardware like cellular modems and WiFi connectivity and, in addition, the inverters used to connect these resources to the grid are gaining increasingly complex capabilities, like providing voltage and frequency support or supporting microgrids. To perform these new functions safely, communications to the device and more complex controls are required. The distributed nature of DER devices combined with their network connectivity and complex controls interfaces present a larger potential attack surface for adversaries looking to create instability in power systems. To address this area of concern, the steps of a cyberattack on DERs have been studied, including the security of industrial protocols, the misuse of the DER interface, and the physical impacts. These different steps have not previously been tied together in practice and not specifically studied for grid-connected storage devices. In this work, we focus on grid-connected batteries. We explore the potential impacts of a cyberattack on a battery to power system stability, to the battery hardware, and on economics for various stakeholders. We then use real hardware to demonstrate end-to-end attack paths exist when security features are disabled or misconfigured. Our experimental focus is on control interface security and protocol security, with the initial assumption that an adversary has gained access to the network to which the device is connected. We provide real examples of the effectiveness of certain defenses. This work can be used to help utilities and other grid-connected battery owners and operators evaluate the severity of different threats and the effectiveness of defense strategies so they can effectively deploy and protect grid-connected storage devices.

25 ENERGY STORAGE↗

A method of hardware qualification for flight by analyses, similarity and integrated testing

The results are described of a study on four pieces of flight hardware from the Saturn 1U and S-4B stages to determine whether the objectives of the formal qualification tests on that hardware could have been obtained within that program by methods other than performing the qualification tests. These methods include qualification by analyses, similarity and integrated testing, i.e., distribution of the objectives among the other tests in the program. It was found that it is feasible to delete the requirements for formal qualification testing provided that it is accomplished early in the program to allow adequate planning for accomplishing the qualification objectives by other means. Additionally, a scorekeeping system was defined that is simple, straightforward, easy to implement. This scorekeeping system provides complete visibility of equivalent qualification status at any point during the program. A set of groundrules for implementing this study was established as a result of findings on the specific items of hardware studied.

Andriulli, J. B.↗

Skylab biomedical hardware development

The development of hardware to support biomedical experimentation and operations in the Skylab vehicle presented unique technical problems. Designs were required to enable the accurate measurement of many varied physiological parameters and to compensate for zero g such that uninhibited equipment operation would be possible. Because of problems that occurred during the orbital workshop launch, special tests were run and new equipment was designed and built for use by the first Skylab crew. Design concepts used in the development of hardware to support cardiovascular, pulmonary, vestibular, body, and specimen mass measuring experiments are discussed. Additionally, major problem areas and the corresponding design solutions, as well as knowledge gained that will be pertinent for future life sciences hardware development, are presented.

Huffstetler, W. J., Jr.↗

Hardware realization of sampled-data controllers

This paper examines the hardware implementation process for digital controllers (filters), beginning with the desired z-domain transfer function of the digital compensator and ending in the selection of a hardware realization scheme. The final hardware realization is shown to be affected by quantization noise, dynamic range considerations, limit cycles, coefficient roundoff, and filter structure. A design example is included to illustrate the implementation process for a digital rate filter for vehicle control of the space shuttle. This paper develops open-loop techniques which may be extended to the closed-loop case.

Nagle, H. T., Jr.↗

Design and evaluation of a fault-tolerant multiprocessor using hardware recovery blocks

A fault-tolerant multiprocessor with a rollback recovery mechanism is discussed. The rollback mechanism is based on the hardware recovery block which is a hardware equivalent to the software recovery block. The hardware recovery block is constructed by consecutive state-save operations and several state-save units in every processor and memory module. When a fault is detected, the multiprocessor reconfigures itself to replace the faulty component and then the process originally assigned to the faulty component retreats to one of the previously saved states in order to resume fault-free execution. A mathematical model is proposed to calculate both the coverage of multi-step rollback recovery and the risk of restart. A performance evaluation in terms of task execution time is also presented.

Lee, Y. H.↗

A fast, programmable hardware architecture for spaceborne SAR processing

The launch of spaceborne SARs during the 1980's is discussed. The satellite SARs require high quality and high throughput ground processors. Compression ratios in range and azimuth of greater than 500 and 150 respectively lead to frequency domain processing and data computation rates in excess of 2000 million real operations per second for C-band SARs under consideration. Various hardware architectures are examined and two promising candidates and proceeds to recommend a fast, programmable hardware architecture for spaceborne SAR processing are selected. Modularity and programmability are introduced as desirable attributes for the purpose of HTSP hardware selection.

Bennett, J. R.↗

Solar array Shuttle flight experiment - Hardware development and testing

This paper reports on the fabrication and ground testing of (a) a large area, light-weight, flexible substrate developmental solar array wing that has been built for NASA-MSFC and of (b) the supporting structure and data acquisition system (DAS) which, with the wing, will be flown in the Shuttle as an experiment in 1984. The experiment will verify the dynamics, thermodynamic, and electrical performance predictions of the array wing and will demonstrate the structural capability of the array wing for Orbiter launch and re-entry environments. The experiment hardware verification program was designed to minimize costs and risk of experiment performance degradation while maintaining Shuttle and crew safety. The previous full-scale wing hardware tests included an extension mast water table test and wing testing for random vibration, thermal vacuum, and acoustic environments. The results of these tests were used to define wing design modifications and to scope the test program for the experiment hardware.

Elms, R. V.↗

Hardware test program for evaluation of baseline range/range rate sensor concept

The Hardware Test Program for evaluation of the baseline range/range rate sensor concept was initiated 11 September 1984. This ninth report covers the period 12 May through 11 June 1885. A contract amendment adding a second phase has extended the Hardware Test Program through 10 December 1985. The objective of the added program phase is to establish range and range measurement accuracy and radar signature characteristics for a typical spacecraft target. Phase I of the Hardware Test Program was designed to reduce the risks associated with the Range/Range Rate (R/R) Sensor baseline design approach. These risks are associated with achieving the sensor performance required for the two modes of operation, the Interrupted CW (ICW) mode for initial acquisition and tracking to close-in ranges, and the CW mode, providing coverage during the final docking maneuver. The risks associated with these modes of operation have to do with the realization of adequate sensitivity to operate to their individual maximum ranges.

Source record↗

Hardware schemes for fast Fourier transform, part 7.4A

Real-time fast fourier transformer (FFT) processing of a MST radar data and cost-effective approaches to hardware FFT generation were studied. Previously devised hardware FFT configurations are described including the estimated number of chips used and the time required to perform a 1024-point FFT. The remaining entries in the table correspond to original designs, which presuppose the availability of a microcomputer and a modestly complicated hardware peripheral. These original designs, all of which implement a radix-4 FFT with twiddle factors, are assigned model numbers to make them easier to refer to.

Stitt, G. R.↗

Access flight hardware design and development

Several items were found to be of immense value in the design and development of the Assembly Concept for Construction of Erectable Space Structures (ACCESS) hardware. The early availability of mock-up and engineering test hardware helped to develop the concept and prove the feasibility of the experiment. The extensive neutral buoyancy testing was invaluable in developing the procedures and timelines, proving that the hardware functioned as intended, and effectively trained the astronauts. The early involvement of the crew systems/astronaut personnel was extremely beneficial in shaping the design to meet the EVA compatibility requirements. Also, the early definition of coupled loads and on-orbit dynamic responses can not be overemphasized due to the relative uncertainty in the magnitude of these loads and their impact on the design.

Rogers, John F.↗

Electronic hardware implementations of neutral networks

This paper examines some of the present work on the development of electronic neural network hardware. In particular, the investigations currently under way at JPL on neural network hardware implementations based on custom VLSI technology, novel thin film materials, and an analog-digital hybrid architecture are reviewed. The availability of such hardware will greatly benefit and enhance the present intense research effort on the potential computational capabilities of highly parallel systems based on neural network models.

Thakoor, A. P.↗

Hardware realization of a baseband processor for a SS-FDMA/TDMA/DAMA system

Hardware implementation of the NASA ACTS baseband processor is described which achieves the system message data handling performance required to perform satellite switching of high-rate baseband data. The hardware meets payload specifications for size, weight, and power. Hardware redundancy applied to critical paths in several functional areas insures that the reliability and life expectancy requirements are fulfilled. The remote reprogrammability of the processor message data handling and routing functions provides system flexibility for dynamic reconfiguration during rapidly changing traffic loads.

Moat, Richard L.↗

Hardware development for the surface tension driven convection experiment aboard the USML-1 spacelab mission

The Surface Tension Driven Convection Experiment is a Space Transportation System flight experiment to study both transient and steady thermocapillary fluid flows aboard the USML-1 Spacelab mission planned for March 1992. Hardware is under development to establish the experimental conditions and perform the specified measurements, for both ground based research and the flight experiment in a Spacelab single rack. Major development areas include an infrared thermal imaging system for surface temperature measurement, a CO2 laser and control system for surface heating, and for flow visualization, a He-Ne laser and optical system in conjunction with an intensified video camera. For ground based work the components of each system were purchased or designed, and tested individually. The three systems will be interfaced with the balance of the experimental hardware and will constitute a working engineering model. A description of the three systems and examples of the component performance is given along with the plans for the development of flight hardware.

Pline, A. D.↗

Transmission delays in hardware clock synchronization

Various methods, both with software and hardware, have been proposed to synchronize a set of physical clocks in a system. Software methods are very flexible and economical but suffer an excessive time overhead, whereas hardware methods require no time overhead but are unable to handle transmission delays in clock signals. The effects of nonzero transmission delays in synchronization have been studied extensively in the communication area in the absence of malicious or Byzantine faults. The authors show that it is easy to incorporate the ideas from the communication area into the existing hardware clock synchronization algorithms to take into account the presence of both malicious faults and nonzero transmission delays.

Shin, Kang G.↗

Hardware development for the Surface Tension Driven Convection Experiment aboard the USML-1 Spacelab mission

The Surface Tension Driven Convection Experiment is a Space Transportation System flight experiment to study both transient and steady thermocapillary fluid flows aboard the USML-1 Spacelab mission planned for March 1992. Hardware is under development to establish the experimental conditions and perform the specified measurements, for both ground based research and the flight experiment in a Spacelab single rack. Major development areas include an infrared thermal imaging system for surface temperature measurement, a CO2 laser and control system for surface heating, and for flow visualization, a He-Ne laser and optical system in conjunction with an intensified video camera. For ground based work the components of each system were purchased or designed, and tested individually. The three systems will be interfaced with the balance of the experimental hardware and will constitute a working engineering model. A description of the three systems and examples of the component performance is given along with the plans for the development of flight hardware.

Pline, A. D.↗

Distributed execution of recovery blocks - An approach for uniform treatment of hardware and software faults in real-time applications

The concept of distributed execution of recovery blocks is examined as an approach for uniform treatment of hardware and software faults. A useful characteristic of the approach is the relatively small time cost it requires. The approach is thus suitable for incorporation into real-time computer systems. A specific formulation of the approach that is aimed at minimizing the recovery time is presented, called the distributed recovery block (DRB) scheme. The DRB scheme is capable of effecting forward recovery while handling both hardware and software faults in a uniform manner. An approach to incorporating the capability for multiprocessing scheme is also discussed. Two experiments aimed at testing the execution efficiency of the scheme in real-time applications have been conducted on two different multimicrocomputer networks. The results clearly indicate the feasibility of achieving tolerance of hardware and software faults in a broad range of real-time computer systems by use of the schemes for distributed execution of recovery blocks.

Kim, K. H.↗

The JPL telerobot operator control station. Part 1: Hardware

The Operator Control Station of the Jet Propulsion Laboratory (JPL)/NASA Telerobot Demonstrator System provides the man-machine interface between the operator and the system. It provides all the hardware and software for accepting human input for the direct and indirect (supervised) manipulation of the robot arms and tools for task execution. Hardware and software are also provided for the display and feedback of information and control data for the operator's consumption and interaction with the task being executed. The hardware design, system architecture, and its integration and interface with the rest of the Telerobot Demonstrator System are discussed.

Kan, Edwin P.↗