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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Optically controlled phased array antenna concepts using GaAs monolithic microwave integrated circuits

The desire for rapid beam reconfigurability and steering has led to the exploration of new techniques. Optical techniques have been suggested as potential candidates for implementing these needs. Candidates generally fall into one of two areas: those using fiber optic Beam Forming Networks (BFNs) and those using optically processed BFNs. Both techniques utilize GaAs Monolithic Microwave Integrated Circuits (MMICs) in the BFN, but the role of the MMIC for providing phase and amplitude variations is largely eliminated by some new optical processing techniques. This paper discusses these two types of optical BFN designs and provides conceptual designs of both systems.

Kunath, R. R.↗
NASA NTRS1983

Modeling of single-event upset in bipolar integrated circuits

The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

Zoutendyk, J. A.↗
NASA NTRS1991

An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits

Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

Lubecke, Victor M.↗
NASA NTRS1988

Tool For Tinning Integrated-Circuit Leads

As many as eight flatpacks held. Tool made of fiberglass boards. Clamps row of flatpacks by their leads so leads on opposite side of packages dipped. After dipping, nuts on boards loosened, flatpacks turned around, nuts retightened, and untinned leads dipped. Strips of magnetic material grip leads of flatpacks (made of Kovar, magnetic iron/nickel/cobalt alloy) while boards repositioned. Micrometerlike screw used to adjust exposed width of magnetic strip to suit dimensions of flatpacks. Holds flatpack integrated circuits so leads tinned. Accommodates several flatpacks for simultaneous dipping of leads in molten solder. Adjusts to accept flatpacks in range of sizes.

Prosser, Gregory N.↗
NASA NTRS2024

Mark I Silicon Carbide Integrated Circuit Test Oven Assembly and Programming Guide

This report provides a parts list, with assembly and programming instructions for building firstgeneration (Mark I) compact test ovens; this oven design is customized for prolonged functional electrical testing of prototype silicon carbide (SiC) devices at temperatures up to 500 °C (932 °F). The general approach of using multiple compact ovens to perform long-term, high-temperature electronics testing efficiently is described in a conference paper (Izadnegahdar, Alain, et al.: Alternative Setup for LongDuration Low-Duty-Cycle 600 °C Ambient Testing of SiC Integrated Circuits. International Microelectronics Assembly and Packaging Society (iMAPS) HiTECH 2021 Technology Crossover Extravaganza, 2021), available at https://ntrs.nasa.gov/citations/20210011676. The new Mark I oven design described here offers several significant improvements over the compact oven described in that paper. For example, it is constructed from commercial off-the-shelf (COTS) components and requires minimal assembly. Much of the work involves drilling holes in the two aluminum project boxes, which contain the control electronics and the oven itself. The cost of components is less than $200 (USD) per oven, which makes constructing multiple ovens affordable. In addition, the two-box design separates the high-temperature heater from the electronics, which keeps the electronics cool, prolonging the lifetime of these components.

high temperature↗
NASA NTRS1992

Scheduling revisited workstations in integrated-circuit fabrication

The cost of building new semiconductor wafer fabrication factories has grown rapidly, and a state-of-the-art fab may cost 250 million dollars or more. Obtaining an acceptable return on this investment requires high productivity from the fabrication facilities. This paper describes the Photo Dispatcher system which was developed to make machine-loading recommendations on a set of key fab machines. Dispatching policies that generally perform well in job shops (e.g., Shortest Remaining Processing Time) perform poorly for workstations such as photolithography which are visited several times by the same lot of silicon wafers. The Photo Dispatcher evaluates the history of workloads throughout the fab and identifies bottleneck areas. The scheduler then assigns priorities to lots depending on where they are headed after photolithography. These priorities are designed to avoid starving bottleneck workstations and to give preference to lots that are headed to areas where they can be processed with minimal waiting. Other factors considered by the scheduler to establish priorities are the nearness of a lot to the end of its process flow and the time that the lot has already been waiting in queue. Simulations that model the equipment and products in one of Texas Instrument's wafer fabs show the Photo Dispatcher can produce a 10 percent improvement in the time required to fabricate integrated circuits.

Kline, Paul J.↗
NASA NTRS1992

Progress in integrated-circuit horn antennas for receiver applications. Part 2: A 90 GHz quasi-integrated horn antenna receiver

A receiver belonging to the family of integrated planar receivers has been developed at 90 GHz. It consists of a planar Schottky-diode placed at the feed of a dipole-probe suspended inside an integrated horn antenna. The measured planar mixer single-sideband conversion loss at 91.2 GHz (LO) with a 200 MHz IF frequency is 8.3dB plus or minus 0.3dB. The low cost of fabrication and simplicity of this design makes it ideal for millimeter and submillimeter-wave receivers.

Ali-Ahmad, Walid Y.↗
NASA NTRS1982

Computer-aided prediction of high-frequency performance limits in silicon bipolar integrated circuits

A circuit model for an existing silicon integrated bipolar junction transistor (IBJT) is used to evaluate presently achievable high frequency circuit performance. The relationship between circuit model and processing parameters are semi-quantitatively explored to make predictions on the frequency response, which can be achieved through realistic device fabrication modifications. A new figure of merit is introduced, which is defined as the signal frequency at which an integrated bipolar junction transistor can deliver a power gain of G. The most sensitive parameter influencing attainable high frequency IBJT performance is base resistance.

Burns, J. L.↗
NASA NTRS1982

A monolithic lead sulfide-silicon MOS integrated-circuit structure

A technique is developed for directly integrating infrared photoconductive PbS detector material with MOS transistors. A layer of chromium, instead of aluminum, is deposited followed by a gold deposition in order to ensure device survival during the chemical deposition of the PbS. Among other devices, a structure was fabricated and evaluated in which the PbS was directly coupled to the gate of a PMOS. The external bias, load, and source resistors were connected and the circuit was operated as a source-follower amplifier. Radiometric evaluations were performed on a variety of different MOSFETs of different geometry. In addition, various detector elements were simultaneously fabricated to demonstrate small element capability, and it was shown that elements of 25 x 25 microns could easily be fabricated. Results of room temperature evaluations using a filtered 700 K black body source yielded a detectivity at peak wavelength of 10 to the 11th cm (root Hz)/W at 100 Hz chopping frequency.

Jhabvala, M. D.↗
NASA NTRS1977

Integrated circuit process and design rule evaluation techniques

A technique is described for determining the applicability of a particular process for the fabrication of large-scale integrated (LSI) circuits. Test arrays were developed to isolate various critical processing steps in a fabrication sequence and a statistical evaluation of these steps was carried out that related yield or success in achieving a desired result to the number of times the results were attempted. It was found that, in general, yield is a sensitive function of physical dimensions as is the packing density of a particular array. It is, therefore, possible to generate an optimum set of physical dimensions or design rules that maximize the expected number of working circuits on a wafer.

Ipri, A. C.↗
NASA NTRS1976

Optimum load device for DMOS integrated circuits

Depletion-mode load devices can be integrated with DMOS transistors without any extra diffusions or ion implantation processing steps by judicious choice of the substrate crystal orientation and resistivity. For low voltage operation line-type 1, 1, 1 crystal orientation should be used. The line-type 1, 1, 1 crystal orientation also yields a higher transconductance for the DMOS transistor than the line-type 1, 0, 0 orientation. The geometry of the load device and the DMOS transistor can be made ratioless to conserve area. Self-aligned gates, hitherto considered incompatible with DMOS transistors, have been incorporated in the structure. The experimental DMOS inverters, using a conservative design, have achieved 4-ns propagation delay, 1.3-V operation, and 2-pJ propagation delay-power dissipation product.

Lin, H. C.↗