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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

SPT-SLIM: Line Intensity Mapping with the South Pole Telescope

Line-intensity mapping (LIM) at millimeter wavelengths is a powerful emerging probe of the large-scale structure of the Universe, but achieving meaningful constraints on cosmological parameters with LIM requires focal planes with orders of magnitudes more detectors than existing instruments. SPT-SLIM is an upcoming experiment to demonstrate LIM observations of CO at 0.5 < z < 2.0 using on-chip spectrometers with kinetic inductance detectors (KIDs), a new technology that enables scaling to the much larger arrays of detectors needed to probe cosmology. I will describe the overall experimental design and specific goals of SPT-SLIM. In addition, I will highlight results of the detector and readout electronics development for SPT-SLIM and the status of the camera integration and commissioning in the lab.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS2003

VLSI design of turbo decoder for integrated communication system on a chip applications

A high-throughput low-power turbo decoder core has been developed for integrated communication system applications such as satellite communications, wireless LAN, digital TV, cable modem, Digital Video Broadcast (DVB), and xDSL systems. The turbo decoder is based on convolutional constituent codes, which outperform all other Forward Error Correction techniques. This turbo decoder core is parameterizable and can be modified easily to fit any size for advanced communication system-on-chip products. The turbo decoder core provides Forward Error Correction of up to 15 Mbits/sec on a 0.13-micron CMOS FPGA prototyping chip at a power of 0.1 watts.

turbo decoder↗
DOE OSTI2022

System-on-chip integrated circuit technology applications on the DIII-D tokamak for multi-field measurements

Several mm-wave diagnostics on the DIII-D tokamak provide multi-scale and multi-dimensional measurements of plasma profile evolution and turbulence fluctuations. Mm-wave fusion plasma diagnostics that adopt system-on-chip integrated circuit technology can provide better space utilization, flexible installation, and improved sensitivity. In order to further extend this technology for additional fusion facilities with a higher toroidal magnetic field, V-band (55–75 GHz) and F-band (90–140 GHz) chips for Microwave Imaging Reflectometer (MIR) and Electron Cyclotron Emission Imaging (ECEI) instruments are developed and tested in the Davis Millimeter Wave Research Center (DMRC). Current measurement data show that correlation between these SoC-based diagnostic instruments with other state-of-the-art diagnostics enables co-located multi-field turbulence fluctuation measurement.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2025

Low‐Loss Far‐Infrared Surface Phonon Polaritons in Suspended SrTiO 3 Nanomembranes

Phonon polaritons (PhPs), excitations arising from the coupling of light with lattice vibrations, enable light confinement and local field enhancement, which is essential for various photonic and thermal applications. To date, PhPs with high confinement and low loss are mainly observed in the mid-infrared regime and mostly in manually exfoliated flakes of van der Waals (vdW) materials. In this work, the existence of low-loss, thickness-tunable phonon polaritons in the far-infrared regime within transferable freestanding SrTiO 3 membranes synthesized through a scalable approach, achieving high figures of merit is demonstrated, which are comparable to the previous record values from the vdW materials. Leveraging atomic precision in thickness control, large dimensions, and compatibility with mature oxide electronics, functional oxide membranes present a promising large-scale 2D platform alternative to vdW materials for on-chip polaritonic technologies in the infrared regime.

functional oxide membranes↗
NASA NTRS1981

Monolithic CCD-array readout

Circuit is self-biasing, with differential current-to-voltage conversion. CMOS current-differencing readout consists of dc-balanced pair of virtual ground stages and current-differencing circuit similar to circuit mirror. Triode multiplier cell replaces test sources to form monolithic configuration. Transistors belonging to selected multiplier cell need to be duplicated for each multiplier within correlator chip. Remaining elements form part of readout and may be scaled as single common readout stage.

Farnsworth, D. L.↗
NASA NTRS1984

An evaluation of the directed flow graph methodology

The applicability of the Directed Graph Methodology (DGM) to the design and analysis of special purpose image and signal processing hardware was evaluated. A special purpose image processing system was designed and described using DGM. The design, suitable for very large scale integration (VLSI) implements a region labeling technique. Two computer chips were designed, both using metal-nitride-oxide-silicon (MNOS) technology, as well as a functional system utilizing those chips to perform real time region labeling. The system is described in terms of DGM primitives. As it is currently implemented, DGM is inappropriate for describing synchronous, tightly coupled, special purpose systems. The nature of the DGM formalism lends itself more readily to modeling networks of general purpose processors.

Snyder, W. E.↗
NASA NTRS1991

Neural Networks Of VLSI Components

Concept for design of electronic neural network calls for assembly of very-large-scale integrated (VLSI) circuits of few standard types. Each VLSI chip, which contains both analog and digital circuitry, used in modular or "building-block" fashion by interconnecting it in any of variety of ways with other chips. Feedforward neural network in typical situation operates under control of host computer and receives inputs from, and sends outputs to, other equipment.

Eberhardt, Silvio P.↗
NASA NTRS1995

A CCD offset guider for the KAO

We describe a focal plane guider for the Kuiper Airborne Observatory which consists of a CCD camera interfaced to an AMIGA personal computer. The camera is made by Photometrics Ltd. and utilizes a Thomson 576 x 384 pixel CCD chip operated in Frame Transfer mode. Custom optics produce a scale of 2.4 arc-sec/pixel, yielding an approx. 12 ft. diameter field of view. Chopped images of stars with HST Guide Star Catalog magnitudes fainter than 14 have been used for guiding at readout rates greater than or equal to 0.5 Hz. The software includes automatic map generation, subframing and zooming, and correction for field rotation when two stars are in the field of view.

Colgan, Sean W. J.↗
DOE OSTI2023

Characterization of superconducting through-silicon vias as capacitive elements in quantum circuits

The large physical size of superconducting qubits and their associated on-chip control structures presents a practical challenge toward building a large-scale quantum computer. In particular, transmons require a high-quality-factor shunting capacitance that is typically achieved by using a large coplanar capacitor. Other components, such as superconducting microwave resonators used for qubit state readout, are typically constructed from coplanar waveguides, which are millimeters in length. Here, we use compact superconducting through-silicon vias to realize lumped-element capacitors in both qubits and readout resonators to significantly reduce the on-chip footprint of both of these circuit elements. We measure two types of devices to show that through-silicon vias are of sufficient quality to be used as capacitive circuit elements and provide a significant reduction in size over existing approaches.

Physics↗
NASA NTRS2012

Reliability Considerations of ULP Scaled CMOS in Spacecraft Systems

NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub-micron region. Decreasing the feature size of CMOS devices not only allows more components to be placed on a single chip, but it increases performance by allowing faster switching (or clock) speeds with reduced power compared to larger scaled devices. Higher performance, and lower operating and stand-by power characteristics of Ultra-Low Power (ULP) microelectronics are not only desirable, but also necessary to meet low power consumption design goals of critical spacecraft systems. The integration of these components in such systems, however, must be balanced with the overall risk tolerance of the project.

reliability↗
DOE OSTI2026

A 3D-Printed Millimeter-Wave Inline Waveguide-to-Coplanar-Waveguide Transition to Enable Dense Spectrometer Arrays for Intensity Mapping Surveys

We present a 3D-printed millimeter-wave, octave-bandwidth, in-line waveguide-to-coplanar-waveguide transition designed to enable focal planes with dense arrays of on-chip spectrometers. These arrays will enable compelling surveys of the large-scale structure of the universe through millimeter-wave intensity mapping. The transition consists of a four-step ridge-waveguide transformer that couples light from a rectangular waveguide onto a coplanar waveguide via an electrical connection made with indium bump bonds. We develop a tolerance-aware optimization approach to identify high-performance transition geometries that are robust to manufacturing variations; the same formulation can be applied to other tolerance-sensitive design problems. We also describe the implementation of a custom apparatus and procedure for bump-bonding a silicon chip to a metallized 3D-printed component. We detail the fabrication of the coplanar waveguide chip and three-dimensional waveguide structure, simulations and metrology of a test device, and room temperature reflectance measurements of this device. The room temperature metrology and reflection measurements are consistent with a model that predicts a coupling efficiency of $\mathord{\sim} 95\%$ at cryogenic temperatures in the 85-170 GHz frequency range.

Stover, Austin [Chicago U.; Chicago U., KICP] (ORC↗
NASA NTRS1972

Packaging concept for LSI beam lead integrated circuits

Development of packaging system for mounting beam lead integrated chip circuit on lead frame is discussed. Process for fabricating large scale integration circuits is described. Diagrams illustrating method of construction are included.

Kennedy, B. W.↗
NASA NTRS1977

Optical integrated-circuit tester

Computer controlled device can check typical medium scale unit in less than one minute. System scans integrated circuit chip with narrow beam of light while simultaneously scanning reference chip.

Micka, E. A.↗
NASA NTRS2014

Novel Epoxy Particulate Composites for Mitigation of Insect Residue Adhesion on Future Aircraft Surfaces

Drag is reduced significantly for airflow over surfaces when laminar flow can be maintained over greater chord lengths, the distance from the leading edge of an airfoil.1 However, surface imperfections, such as chipped paint, scratches, and events that change topography on a microscopic scale can introduce airflow instabilities resulting in premature transition to turbulent flow.1 Although many of these surface imperfections can be avoided with proper maintenance, advanced materials, and advanced manufacturing practices, topographical surface anomalies arising during flight from insect impacts cannot be controlled and can influence laminar flow stability. Practical solutions to this operational challenge need to be developed for future aircraft to have full advantage of laminar flow designs that improve fuel efficiency.2 Researchers have investigated various methods to mitigate insect residue adhesion for decades.3 Although several techniques have demonstrated efficacy including mechanical scrapers, active liquid discharge systems, and sacrificial paper coatings, they have not been commercially implemented due to increased manufacturing and operational complexity, environmental impact, and weight penalties. Coatings offer a simple route for passive insect residue adhesion prevention without many of the challenges associated with maintenance of laminar flow.4 In our previous work, we determined that most commercially available materials were not effective at insect residue adhesion.5 We also identified improvements when both surface energy could be controlled by surface modifying agents and the topography could be altered through the use of micron-sized and nanometer-sized filler materials.6 In this work, these general principles were applied to an epoxy system to evaluate the behavior of the surface modifying agent, a fluorinated alkyl ether oligomer, on surface energy and insect residue adhesion properties.

Wohl, Christopher J.↗
NASA NTRS2023

2023 Astrophotonics Roadmap: Pathways to Realizing Multi-Functional Integrated Astrophotonic Instruments

Photonic technologies offer numerous functionalities that can be used to realize astrophotonic instruments. The most spectacular example to date is the ESO Gravity instrument at the Very Large Telescope in Chile that combines the light-gathering power of four 8 m telescopes through a complex photonic interferometer. Fully integrated astrophotonic devices stand to offer critical advantages for instrument development, including extreme miniaturization when operating at the diffraction-limit, as well as integration, superior thermal and mechanical stabilization owing to the small footprint, and high replicability offering significant cost savings. Numerous astrophotonic technologies have been developed to address shortcomings of conventional instruments to date, including for example the development of photonic lanterns to convert from multimode inputs to single mode outputs, complex aperiodic fiber Bragg gratings to filter OH emission from the atmosphere, complex beam combiners to enable long baseline interferometry with for example, ESO Gravity, and laser frequency combs for high precision spectral calibration of spectrometers. Despite these successes, the facility implementation of photonic solutions in astronomical instrumentation is currently limited because of (1) low throughputs from coupling to fibers, coupling fibers to chips, propagation and bend losses, device losses, etc, (2) difficulties with scaling to large channel count devices needed for large bandwidths and high resolutions, and (3) efficient integration of photonics with detectors, to name a few. In this roadmap, we identify 24 key areas that need further development. We outline the challenges and advances needed across those areas covering design tools, simulation capabilities, fabrication processes, the need for entirely new components, integration and hybridization and the characterization of devices. To realize these advances the astrophotonics community will have to work cooperatively with industrial partners who have more advanced manufacturing capabilities. With the advances described herein, multi-functional integrated instruments will be realized leading to novel observing capabilities for both ground and space based platforms, enabling new scientific studies and discoveries.

astrophotonics↗
NASA NTRS1992

Ultra-dense magnetoresistive mass memory

This report details the progress and accomplishments of Nonvolatile Electronics (NVE), Inc., on the design of the wafer scale MRAM mass memory system during the fifth quarter of the project. NVE has made significant progress this quarter on the one megabit design in several different areas. A test chip, which will verify a working GMR bit with the dimensions required by the 1 Meg chip, has been designed, laid out, and is currently being processed in the NVE labs. This test chip will allow electrical specifications, tolerances, and processing issues to be finalized before construction of the actual chip, thus providing a greater assurance of success of the final 1 Meg design. A model has been developed to accurately simulate the parasitic effects of unselected sense lines. This model gives NVE the ability to perform accurate simulations of the array electronic and test different design concepts. Much of the circuit design for the 1 Meg chip has been completed and simulated and these designs are included. Progress has been made in the wafer scale design area to verify the reliable operation of the 16 K macrocell. This is currently being accomplished with the design and construction of two stand alone test systems which will perform life tests and gather data on reliabiliy and wearout mechanisms for analysis.

Daughton, J. M.↗
DOE OSTI2023

COLLABORATIVE DEVELOPMENT PROJECTS - PHOTONIC MEMORY CONTROLLER MODULE (P-MCM)

As computational density for high-performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. A consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high-performance memory controller IP development – to collaboratively develop a commercialization path for a Photonic Memory Controller Module (P-MCM).

97 MATHEMATICS AND COMPUTING↗