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At least 253 records · Page 14
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Complementary Paired G4FETs as Voltage-Controlled NDR Device

It is possible to synthesize a voltage-controlled negative-differential-resistance (NDR) device or circuit by use of a pair of complementary G4FETs (four-gate field-effect transistors). [For more information about G4FETs, please see the immediately preceding article]. As shown in Figure 1, the present voltage-controlled NDR device or circuit is an updated version of a prior NDR device or circuit, known as a lambda diode, that contains a pair of complementary junction field-effect transistors (JFETs). (The lambda diode is so named because its current-versus- voltage plot bears some resemblance to an upper-case lambda.) The present version can be derived from the prior version by substituting G4FETs for the JFETs and connecting both JFET gates of each G4FET together. The front gate terminals of the G4FETs constitute additional terminals (that is, terminals not available in the older JFET version) to which one can apply control voltages VN and VP. Circuits in which NDR devices have been used include (1) Schmitt triggers and (2) oscillators containing inductance/ capacitance (LC) resonant circuits. Figure 2 depicts such circuits containing G4FET NDR devices like that of Figure 1. In the Schmitt trigger shown here, the G4FET NDR is loaded with an ordinary inversion-mode, p-channel, metal oxide/semiconductor field-effect transistor (inversion-mode PMOSFET), the VN terminal of the G4FET NDR device is used as an input terminal, and the input terminals of the PMOSFET and the G4FET NDR device are connected. VP can be used as an extra control voltage (that is, a control voltage not available in a typical prior Schmitt trigger) for adjusting the pinch-off voltage of the p-channel G4FET and thereby adjusting the trigger-voltage window. In the oscillator, a G4FET NDR device is loaded with a conventional LC tank circuit. As in other LC NDR oscillators, oscillation occurs because the NDR counteracts the resistance in the tank circuit. The advantage of this G4FET-NDR LC oscillator over a conventional LC NDR oscillator is that one can apply a time-varying signal to one of the extra control input terminals (VN or VP) to modulate the conductance of the NDR device and thereby amplitude-modulate the output signal.

Mojarradi, Mohammad↗
DOE OSTI2021

Heterometallic Actinide-Containing Photoresponsive Metal-Organic Frameworks: Dynamic and Static Tuning of Electronic Properties

Acquiring fundamental knowledge of properties of actinide-based materials is a necessary step to create new possibilities for addressing the current challenges in the nuclear energy and nuclear waste sectors. Here in this report, we established a photophysics–electronics correlation for actinide-containing metal-organic frameworks (An-MOFs) as a function of excitation wavelength, for the first time. A stepwise approach for dynamically modulating electronic properties was applied for the first time towards actinide-based heterometallic MOFs through integration of photochromic linkers. Optical cycling, modeling of density of states near the Fermi edge, conductivity measurements, and photoisomerization kinetics were employed to shed light on the process of tailoring optoelectronic properties of An-MOFs. Furthermore, the first photochromic MOF-based field-effect transistor, in which the field-effect response could be changed through light exposure, was constructed. As a demonstration, the change in current upon light exposure was sufficient to operate a two-LED fail-safe indicator circuit.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Dielectrophoresis-Based Positioning of Carbon Nanotubes for Wafer-Scale Fabrication of Carbon Nanotube Devices

In this paper, we report the wafer-scale fabrication of carbon nanotube field-effect transistors (CNTFETs) with the dielectrophoresis (DEP) method. Semiconducting carbon nanotubes (CNTs) were positioned as the active channel material in the fabrication of carbon nanotube field-effect transistors (CNTFETs) with dielectrophoresis (DEP). The drain-source current (IDS) was measured as a function of the drain-source voltage (VDS) and gate-source voltage (VGS) from each CNTFET on the fabricated wafer. The IDS on/off ratio was derived for each CNTFET. It was found that 87% of the fabricated CNTFETs was functional, and that among the functional CNTFETs, 30% of the CNTFETs had an IDS on/off ratio larger than 20 while 70% of the CNTFETs had an IDS on/off ratio lower than 20. The highest IDS on/off ratio was about 490. The DEP-based positioning of carbon nanotubes is simple and effective, and the DEP-based device fabrication steps are compatible with Si technology processes and could lead to the wafer-scale fabrication of CNT electronic devices.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2020

Ion Exchange Gels Allow Organic Electrochemical Transistor Operation with Hydrophobic Polymers in Aqueous Solution

Conjugated-polymer-based organic electrochemical transistors (OECTs) are being studied for applications ranging from biochemical sensing to neural interfaces. While new polymers that interface digital electronics with the aqueous chemistry of life are being developed, the majority of high-performance organic transistor materials are poor at transporting biologically relevant ions. Here, the operating mode of an organic transistor is changed from that of an electrolyte-gated organic field-effect transistor (EGOFET) to that of an OECT by incorporating an ion exchange gel between the active layer and the aqueous electrolyte. This device works by taking up biologically relevant ions from solution and injecting more hydrophobic ions into the active layer. Using poly[2,5-bis(3-tetradecylthiophen-2-yl) thieno[3,2-b]thiophene] as the active layer and a blend of an ionic liquid, 1-butyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, and poly(vinylidene fluoride-co-hexafluoropropylene) as the ion exchange gel, four orders of magnitude improvement in device transconductance and a 100-fold increase in kinetics are demonstrated. The ability of the ion-exchange-gel OECT to record biological signals by measuring the action potentials of a Venus flytrap is demonstrated. These results show the possibility of using interface engineering to open up a wider palette of organic semiconductors as OECTs that can be gated by aqueous solutions.

Bischak, Connor G.↗
NASA NTRS1994

Particle sensor array

A particle sensor array which in a preferred embodiment comprises a static random access memory having a plurality of ion-sensitive memory cells, each such cell comprising at least one pull-down field effect transistor having a sensitive drain surface area (such as by bloating) and at least one pull-up field effect transistor having a source connected to an offset voltage. The sensitive drain surface area and the offset voltage are selected for memory cell upset by incident ions such as alpha-particles. The static random access memory of the present invention provides a means for selectively biasing the memory cells into the same state in which each of the sensitive drain surface areas is reverse biased and then selectively reducing the reversed bias on these sensitive drain surface areas for increasing the upset sensitivity of the cells to ions. The resulting selectively sensitive memory cells can be used in a number of applications. By way of example, the present invention can be used for measuring the linear energy transfer of ion particles, as well as a device for assessing the resistance of CMOS latches to Cosmic Ray induced single event upsets. The sensor of the present invention can also be used to determine the uniformity of an ion beam.

Buehler, Martin G.↗
DOE OSTI2025

High Mobility and Electrostatics in GeSn Quantum Wells With SiGeSn Barriers

GeSn is an emerging material with potential applications in next‐generation integrated optoelectronics and quantum information processing. While GeSn/SiGeSn quantum wells exhibit promising optical properties, their electrical transport characteristics and governing electrostatics in gated structures remain unexplored. Heterostructure field‐effect transistors are fabricated using GeSn/SiGeSn quantum wells and electronic transport properties of 2D holes are characterized. At 2 K, heterostructure field‐effect transistors with well/barrier compositions of Ge 0.945 Sn 0.055 /Si 0.03 Ge 0.93 Sn 0.04 and Ge 0.9 Sn 0.1 /Si 0.017 Ge 0.927 Sn 0.056 , show peak mobilities of 9000 and 19 000 cm 2 /Vs, respectively, the latter setting a record for the highest mobility reported for GeSn quantum wells with a Sn concentration around 6 % or greater. Remarkably, at low carrier densities, devices with a SiGeSn barrier exhibit mobilities several times higher than previously reported for GeSn quantum wells with a Ge barrier. This higher mobility contrasts with the expectation that alloy scattering from the barrier would reduce carrier mobility. Two mechanisms based on atom probe tomography data analyses are proposed: i) unintentionally improved SiGeSn/GeSn interface and/or ii) reduced alloy scattering from short‐range order. Significant current–voltage hysteresis is observed, with the effective threshold gate voltage shifting by more than 5 V, attributed to non‐equilibrium trapped charge at various interfaces within the SiGeSn heterostructure.

GeSn↗
NASA NTRS1986

Overcash, D. R.

The objectives of this investigation were to determine the characteristics of semiconductor devices at low temperatures. The output characteristics of several currently available semiconductor devices and devices fabricated at Marshall Space Flight Center were measured over a range of gate voltages. Large variations in low-temperature performance, not only from type to type, but from field effect transistor (FET) to FET of the same type were obtained. By increasing the carrier concentrations at low temperatures through extra heavy doping, metal oxide semiconductor field effect transistor (MOSFET) device was fabricated that operated at 4.2K. To verify the low-temperature operation of a heavily doped device, this procedure was repeated. Their noise spectrum was analyzed at 4.2K. Suggestions were made as to possible fabrication methods, techniques, and other semiconductor materials that might improve the device charactersitics at low temperatures. A procedure for using an electric field to drift dopants through the insulating oxide to produce a very thin, heavily doped region under the gate of a MOSFET was initiated. Capacitance s a function of voltage plots was suggested as a method for determining the level of dopant drift.

Source record↗
NASA NTRS2008

Disabling CNT Electronic Devices by Use of Electron Beams

Bombardment with tightly focused electron beams has been suggested as a means of electrically disabling selected individual carbon-nanotubes (CNTs) in electronic devices. Evidence in support of the suggestion was obtained in an experiment in which a CNT field-effect transistor was disabled (see figure) by focusing a 1-keV electron beam on a CNT that served as the active channel of a field-effect transistor (FET). Such bombardment could be useful in the manufacture of nonvolatile-memory circuits containing CNT FETs. Ultimately, in order to obtain the best electronic performances in CNT FETs and other electronic devices, it will be necessary to fabricate the devices such that each one contains only a single CNT as an active element. At present, this is difficult because there is no way to grow a single CNT at a specific location and with a specific orientation. Instead, the common practice is to build CNTs into electronic devices by relying on spatial distribution to bridge contacts. This practice results in some devices containing no CNTs and some devices containing more than one CNT. Thus, CNT FETs have statistically distributed electronic characteristics (including switching voltages, gains, and mixtures of metallic and semiconducting CNTs). According to the suggestion, by using a 1-keV electron beam (e.g., a beam from a scanning electron microscope), a particular nanotube could be rendered electrically dysfunctional. This procedure could be repeated as many times as necessary on different CNTs in a device until all of the excess CNTs in the device had been disabled, leaving only one CNT as an active element (e.g., as FET channel). The physical mechanism through which a CNT becomes electrically disabled is not yet understood. On one hand, data in the literature show that electron kinetic energy >86 keV is needed to cause displacement damage in a CNT. On the other hand, inasmuch as a 1-keV beam focused on a small spot (typically a few tens of nanometers wide) deposits a significant amount of energy in a small volume, the energy density may suffice to thermally induce structural and/or electronic changes that disable the CNT. Research may be warranted to investigate this effect in detail.

Petkov, Mihail↗
DOE OSTI2026

Growth of Low-Defect WSe 2 Film via High-Purity van der Waals Crystal Precursor

Two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDs) exhibit exceptional electrical and optical properties, empowering their promising prospects for future nanoelectronics. Despite major advances in n-type 2D semiconductors, the field has yet to synthesize high-mobility p-type 2D TMDs, in particular WSe 2 , and systematically query the influence of defects. In this study, we unveil the pivotal role of substitutional impurity defects vis-à-vis the precursor used and growth method employed in defining the quality of 2D p-type WSe 2 . Density functional theory calculations suggest the adverse effect of Fe-, Co-, Ni- and Si-substituted W impurity defects on the mobility of WSe 2 , whereas defects such as O-, S-substituted Se and Mo-substituted W pose negligible impact. Guided by the theory, we pinpoint van der Waals (vdW) crystals, commonly used in mechanical exfoliation, as the optimal precursor, and develop a facile vdW crystal physical vapor deposition (PVD) method to grow high-purity monolayer 2D WSe 2 film (VPVD-WSe 2 ) that is continuous across a centimeter scale. A suite of spectroscopies confirms the markedly reduced defect density of the as-synthesized WSe 2 compared to those by typical chemical vapor deposition methods, and by PVD with commercial or hydrothermal precursors. Scanning tunneling microscopy further evidence the ultralow substitutional impurity defect density of VPVD-WSe 2 , greatly outperforming the control samples and approaching the mechanically exfoliated counterparts. The VPVD-WSe 2 based field-effect transistors exhibit notable electrical performance with record-high field-effect hole mobility up to 112 cm 2 V –1 s –1 at room temperature, exceeding the best-reported monolayer WSe 2 synthesized by chemical vapor deposition and rivaling the mechanically exfoliated 2D WSe 2 flakes.

WSe2↗
NASA NTRS2008

SiC JFET Transistor Circuit Model for Extreme Temperature Range

A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.

Neudeck, Philip G.↗
NASA NTRS2005

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

MacLeod, Todd C.↗
NASA NTRS1985

Measurement of the characteristic X ray of oxygen and other ultrasoft X rays using mercuric iodide detectors

This letter reports the detection and resolution of the characteristic X-ray of oxygen at 523 eV and other ultrasoft X-rays (photons energy less than 1 keV) using radiation detectors fabricated from the compound semi-insulator mercuric iodide (HgI2). These detectors are capable of operation at room ambient but in these experiments were slightly cooled using a Peltier element to 0 C. A pulsed light feedback preamplifier with a Peltier element cooled (to -30 deg) first stage field-effect transistor was used to amplify signals from the detector. Overall system noise level was 185 eV (full width at half-maximum) limited by the temperature of the first stage field-effect transistor. With optimal cooling of this element the characteristic X-ray of carbon at 282 eV should be measurable. These results would seem to be important in measurement of biological samples in electron column instruments.

Iwanczyk, J. S.↗
NASA NTRS2011

Method for Providing Semiconductors Having Self-Aligned Ion Implant

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Neudeck, Philip G.↗
NASA NTRS2014

Method for Providing Semiconductors Having Self-Aligned Ion Implant

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Neudeck, Philip G.↗
NASA NTRS2012

A Comparison of High-Energy Electron and Cobalt-60 Gamma-Ray Radiation Testing

In this paper, a comparison between the effects of irradiating microelectronics with high energy electrons and Cobalt-60 gamma-rays is examined. Additionally, the effect of electron energy is also discussed. A variety of part types are investigated, including discrete bipolar transistors, hybrids, and junction field effect transistors

Boutte, Alvin J.↗
NASA NTRS1991

Stacked-Gate FET's For Analog Memory Elements

Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.

Thakoor, Anilkumar P.↗
DOE OSTI2024

A portable and reusable sensor system based on graphene for real-time and sensitive detection of lead ions in water

Long-term exposure to Pb 2+ can cause irreversible damage to the nervous, cardiovascular, and reproductive systems. Therefore, developing a fast and sensitive detection system capable of monitoring minuscule concentrations of Pb 2+ is essential. In this study, we demonstrated a fully portable sensor system enabling rapid, sensitive, and real-time monitoring of Pb 2+ . The sensor system adopted the remote-gate field-effect transistor (RGFET) detection scheme and was easy to operate, even for non-experts. The sensor system comprised two printed circuit boards (PCBs): a sensor PCB with a remote-gate electrode and an analyzer PCB with a metal-oxide-semiconductor field-effect transistor (MOSFET) transducer and peripheral electronics to manage sensor signals. To achieve a high sensitivity for Pb 2+ , we utilized graphene ink drop-casted on the sensor PCB as a sensing membrane. The graphene film was easy to deposit and remove, enabling the sensor PCB to be reused multiple times. The sensor system was further linked to a smartphone application that instantly monitors the sensor response, allowing for rapid point-of-use detection. The sensor exhibited a high sensitivity of 21.7% when the limit of detection (LOD) value of 1 nM (∼0.2 ppb) was detected, and the typical detection time for each sample was approximately 60 seconds. This portable sensor system advances sensing technologies and could potentially supplement expensive, laborious conventional sensing equipment.

54 ENVIRONMENTAL SCIENCES↗