FPGA Mitigation Strategies for Critical Applications
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Traditional design methodology dictates that an instrument electronics platform should consist of a printed circuit board (PCB)—often multiple boards—populated with many components and support electronics. More specifically, each subsystem is composed of numerous integrated circuits (ICs) spread across the board(s), connected with innumerable traces and wires. Additionally, it is often the case that the hardware and software design teams are quite separated—the hardware team designs a board and hands it to a software team, who must then deal with any hardware quirkiness and may need to rewrite software due to inadequately defined interfaces...
We present low-cost and effective methods and results for high levels of Total Ionizing Dose testing performed on the Xilinx Kintex UltraScale (20nm) Field-Programmable Gate Array evaluation board using 60Co and 2 MeV electron sources.
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Being able to learn from complex data with phase information is imperative for many signal processing applications. Today’s real-valued deep neural networks (DNNs) have shown efficiency in latent information analysis but fall short when applied to the complex domain. Deep complex networks (DCN) , in contrast, can learn from complex data, but have high computational costs; therefore, they cannot satisfy the instant decision making requirements of many deployable systems dealing with short observations or short signal bursts. Recent, Binarized Complex Neural Network (BCNN), which integrates DCNs with binarized neural networks (BNN), shows great potential in classifying complex data in real-time. In this paper, we propose a structural pruning based accelerator of BCNN, which is able to provide more than 5000 frames/s inference throughput on edge devices. The high performance comes from both the algorithm and hardware sides. On the algorithm side, we conduct structural pruning to the original BCNN models and obtain 20 × pruning rates with negligible accuracy loss; on the hardware side, we propose a novel 2D convolution operation accelerator for the binary complex neural network. Experimental results show that the proposed design works with over 90% utilization and is able to achieve the inference throughput of 5882 frames/s and 4938 frames/s for complex NIN-Net and ResNet-18 using CIFAR-10 dataset and Alveo U280 Board.
In high energy physics experiment trigger systems, block memories are utilized for various purposes, especially in indexed searching algorithms. It is often demanded to globally reset all memory locations between different events which is a feature not supported in regular block memories. Another common demand is to be able to update the contents in any memory location in a single clock cycle. These two demands can be fulfilled with registers but the cost of using registers for large memory is unaffordable. In this paper, a register-like block memory design scheme is described, which allows updating memory locations in single clock cycle and effectively refreshing entire memory within a single clock. The implementation and test results are presented.
Abstract not provided.
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