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A system for automatically inspecting an integrated circuit was developed. A device for shining a scanning narrow light beam at an integrated circuit to be inspected and another light beam at an accepted integrated circuit was included. A pair of photodetectors that receive light reflected from these integrated circuits, and a comparing system compares the outputs of the photodetectors.
Those factors affecting the cost of electronic subsystems utilizing LSI microcircuits were determined and the most efficient methods for low cost packaging of LSI devices as a function of density and reliability were developed.
Mathematical cost factors were generated for both hybrid microcircuit and printed wiring board packaging methods. A mathematical cost model was created for analysis of microcircuit fabrication costs. The costing factors were refined and reduced to formulae for computerization. Efficient methods were investigated for low cost packaging of LSI devices as a function of density and reliability. Technical problem areas such as wafer bumping, inner/outer leading bonding, testing on tape, and tape processing, were investigated.
The BANNING MOS design system is presented. It complements rather than supplant the normal design activities associated with the design and fabrication of low-power digital electronic equipment. BANNING is user-oriented and requires no programming experience to use effectively. It provides the user a simulation capability to aid in his circuit design and it eliminates most of the manual operations involved in the layout and artwork generation of integrated circuits. An example of its operation is given and some additional background reading is provided.
The 300 C electronics technology based on JFET thick film hybrids was tested up to 10 to the 9th power rad gamma (Si) and 10 to the 15th power neutrons/sq cm. Circuits and individual components from this technology all survived this total dose although some devices required 1 hour of annealing at 200 or 300 C to regain functionality. This technology used with real time annealing should function to levels greater than 10 to the 10th power rad gamma and 10 to the 16th power n/sq cm.
Improved qualification standards and test procedures for epoxy adhesives used in assembly of high-reliability hybrid microcircuits listed in new report. Objective of standards to resolve problems in areas of outgassing, bond shear strength, corrosivity, volume resistivity, ionic impurities, electrical stability, and frequency of qualification testing. pp
A formalism for target fragment transport is presented with application to energy loss spectra in thin silicon devices. Predicted results are compared to experiments with the surface barrier detectors of McNulty et al. The intranuclear cascade nuclear reaction model does not predict the McNulty experimental data for the highest energy events. A semiempirical nuclear cross section gives an adequate explanation of McNulty's experiments. Application of the formalism to specific electronic devices is discussed.
The use of diamondlike carbon (DLC) as a protective coating in harsh environments is addressed. There are three topics presented. The first is a description of the preparation of DLC on seven different infrared transmitting materials, and the possibility of using DLC as an antireflecting coating at commonly used wavelengths. DLC doesn't bond easily to all materials, and special techniques for bonding are presented. The second topic deals with how well DLC will protect a substrate from moisture penetration. This is an important aspect in numerous uses of DLC, including both infrared optics and integrated circuits. The third topic is the effect of particulate impact on film performance and integrity.
An ongoing program on microfabricated field-emitter arrays has produced a gated field-emitter tip structure with submicrometer dimensions and techniques for fabricating emitter arrays with tip packaging densities of up to 1.5 x 10 exp 7 tips/sq cm. Arrays have been fabricated over areas varying from a few micrometers up to 13 cm in diameter. Very small overall emitter size, materials selection, and rigorous emitter-tip processing procedures have contributed to reducing the potential required for field emission to tens of volts. Emission current densities of up to 100 A/sq cm have been achieved with small arrays of tips, and 100-mA total emission is commonly produced with arrays 1 mm in diameter containing 10,000 tips. Transconductances of 5.0 micro-S per tip have been demonstrated, indicating that 50 S/sq cm should be achievable with tip densities of 10 exp 7 tips/sq cm. Details of the cathode arrays and a variety of performance characteristics are discussed.
The JPL CRRES chip was designed and fabricated in 1985 and included in the CRRES MEP. MOSFET Matrix results show the effect of shielding on radiation-induced MOSFET threshold voltage shifts and channel mobility degradation. Shielded (middle board) MOSFETs have a threshold-voltage damage factor that is approximately three orders of magnitude smaller than would be estimated from Co-60 ground tests. Unshielded (outer board) MOSFETs have a threshold-voltage damage factor that would be estimated from Co-60 ground tests. Temperature swings as large as 23 C with a 22.5 orbit periodicity affected the MOSFET data and were removed from the data in order to reveal the radiation effects. This experiment demonstrated the feasibility of characterizing MOSFETs in a matrix, thus reducing the complexity and mass of the experiment.
Custom-made single-chip complementary metal-oxide semiconductor (CMOS) integrated circuit designed to reveal effects of ionizing radiation on itself and similar integrated circuits. Potential terrestrial use: safety-oriented monitoring of ionizing radiation at nuclear powerplants, nuclear-waste sites, and the like.
The general theory of conduction in a piezoresistive material subjected to temperature change is derived and the basic equations needed to design and apply test chips for thermal stress measurement are established. A general expression is obtained for the resistance changes which occur in an arbitrarily oriented 1D filamentary conductor subjected to general 3D stress states and arbitrary temperature changes. The derived formula is valid for crystals such as silicon which have cubic symmetry and diamond lattice structures. Basic equations are presented for the resistance changes experienced by stressed in-plane resistors fabricated on (100) silicon wafers. The established theory is applied to a simple two-element sensor rosette. A test chip containing this rosette configuration is designed and fabricated, and a suitable calibration system is constructed.
Data from a MOSFET matrix on two JPL (CIT Jet Propulsion Laboratory) CRRES (Combined Release and Radiation Effects Satellite) chips, each behind different amounts of shielding, are presented. Space damage factors are nearly identical to ground test values for pMOSFETs. The results from neighboring rows of MOSFETs show similar radiation degradation. The SRD (Space Radiation Dosimeter) is used to measure the total dose accumulated by the JPL chips. A parameter extraction algorithm that does not underestimate threshold voltage shifts is used. Temperature effects are removed from the MOSFET data.
Qualification procedures for complex integrated circuits are being developed under a U.S. government program known as Qualified Manufacturing Lines (QML). This effort is focused on circuits designed by IC manufacturers and has not addressed application specific IC's (ASIC's) designed at system houses. The qualification procedures described here are intended to be responsive to the needs of system houses who design their own ASIC's and have them fabricated at Silicon foundries. A particular focus of this presentation will be the use of the TID (total Ionizing Dose) Chip to evaluate CMOS foundry processes and to provide parameters for circuit simulators. This chip is under development as a standard chip for qualifying the total dose aspects of ASIC's. The benefits of standardization are that the results will be well understood and easy to interpret. Data is presented and compared for 1.6 micron and 3.0 micron CMOS. The data shows that 1.6 micron CMOS is significantly harder than 3.0 micron CMOS. Two failure modes are explored: (1) the radiation-induced degradation of timing delays; and (2) radiation-induced leakage currents.
Engineering neural network systems are best known for their abilities to adapt to the changing characteristics of the surrounding environment by adjusting system parameter values during the learning process. Rapid advances in analog current-mode design techniques have made possible the implementation of major neural network functions in custom VLSI chips. An electrically programmable analog synapse cell with large dynamic range can be realized in a compact silicon area. New designs of the synapse cells, neurons, and analog processor are presented. A synapse cell based on Gilbert multiplier structure can perform the linear multiplication for back-propagation networks. A double differential-pair synapse cell can perform the Gaussian function for radial-basis network. The synapse cells can be biased in the strong inversion region for high-speed operation or biased in the subthreshold region for low-power operation. The voltage gain of the sigmoid-function neurons is externally adjustable which greatly facilitates the search of optimal solutions in certain networks. Various building blocks can be intelligently connected to form useful industrial applications. Efficient data communication is a key system-level design issue for large-scale networks. We also present analog neural processors based on perceptron architecture and Hopfield network for communication applications. Biologically inspired neural networks have played an important role towards the creation of powerful intelligent machines. Accuracy, limitations, and prospects of analog current-mode design of the biologically inspired vision processing chips and cellular neural network chips are key design issues.
The purpose of this JTEC study is to evaluate Japan's electronic manufacturing and packaging capabilities within the context of global economic competition. To carry out this study, the JTEC panel evaluated the framework of the Japanese consumer electronics industry and various technological and organizational factors that are likely to determine who will win and lose in the marketplace. This study begins with a brief overview of the electronics industry, especially as it operates in Japan today. Succeeding chapters examine the electronics infrastructure in Japan and take an in-depth look at the central issues of product development in order to identify those parameters that will determine future directions for electronic packaging technologies.
Single event phenomena in biological organisms are compared with similar phenomena in microeletronic circuits and the similarities and differences are discussed. Both types of phenomena appear to obey the same model, at least to first order. The general applicability of this first-order model appears to reflect the need to operate despite the noise inherent in the storage and processing of information within microscopic volume elements. Arrays of p-n junctions, each having dimensions of a few microns, are proposed as solid state microdosimeters.
The motor/encoder (henceforth referred to as the UUT) test sequence began with a baseline functional evaluation, which demonstrated that the motor satisfied the operating torque, cogging torque, winding resistance, and mechanical requirements of SOW. In addition, the encoder electrical requirements were verified, as well as the alignment of the encoder outputs relative to the motor shaft position. There were no discrepancies observed in this portion of the test. The UUT was then exposed to a number of environments, including thermal vacuum, thermal cycling, random and sine vibration, and mechanical shock. During the thermal environments, the performance of the UUT under load was verified at specified points in the cycles, as described in ATP 20049. In addition, the UUT was bench tested between the two thermal environments. No anomalies were observed during the thermal tests. The vibration and shock tests were performed by East-West Technology Corporation, West Babylon, New York. The UUT was delivered to the lab in a sealed vibration fixture in order to maintain the cleanliness levels required by the SOW. In addition, a three ounce load was attached to the motor shaft. The attachment method of this load caused damage to the shaft and bearing during random vibration of S/N 0003 on April 28, 1995, and is described further in NCR 00168.