SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
We design a modular FPGA (field-programmable gate array) based system called QubiC to control and measure a superconducting quantum processing unit. The system includes room temperature electronics hardware, FPGA gateware, and engineering software.
CAL-BPM is the firmware code base of the Advanced Light Source (ALS) Beam Position Monitor (BPM) Field Programmable Gate Array (FPGA) based electronics.
CAL-BPM is the firmware code base of the Advanced Light Source (ALS) Beam Position Monitor (BPM) Field Programmable Gate Array (FPGA) based electronics.
SAND2024-08598O The Quantum Instrumentation Control Kit Defect Arbitrary Waveform Generator (QICKDAWG) characterizes nitrogen-vacancy centers in diamond and other defects. It does this by using a radio frequency system-on-a-chip (RFSoC) field programmable gate array (FPGA). QICKDAWG synthesizes microwave pulses from the RFSoC to change the spin state of the defects. The software also allows for laser control using the RFSoC, which optically pumps defects. Ultimately, QICKDAWG supports the implementation of RFSoC FPGAs in defect characterization. This replaces the slow, expensive, traditional hardware, thus lowering the cost and time for defect characterization. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.
Network intrusion detection systems (NIDS) are commonplace in network security but they frequently employ algorithms that are computational demanding requiring hardware and software with significant power requirements. Two examples of such resource-intensive algorithms used for network security are regular expression matching and broader signature pattern matching which are commonly used in deep packet inspection (DPI). Network security algorithms that have large power requirements may be a challenge for low-power internet-of-things (IoT) environments, which generally lack the power resources to implement complex security measures like computationally expensive DPI at the edge. Furthermore, IoT environments incorporating 5G standalone networks have network latency constraints beyond just power that make DPI at the edge even more difficult. Programmable logic is ideally suited for machine learning inference for DPI because of its deep instruction level parallelism and single-cycle memory access. Machine learning approaches for DPI have been explored before using the programmable logic of field programmable gate arrays (FPGA) as a potential solution for NIDS approaches that would be power-suitable for IoT. However, those previous programmable logic NIDS approaches utilize either a supervised or unsupervised learning model. Sentinel utilizes the ensemble of these two machine learning approaches known as a semi-supervised approach which has shown promise in NIDS implementations. Sentinel provides a programmable logic implementation of a semi-supervised approach for DPI which operates at much lower power and latency than a GPU implementation with negligible loss of accuracy due to quantization through a logistic regressor.
This IP provides a comprehensive set of code generators for various floating-point units (FPUs) essential for integrated circuit design and integration, targeting a broad spectrum of applications, including machine learning and scientific computing. The suite includes FP adders, multipliers, subtractors, dividers, reciprocals, exponentials, square roots, trigonometric functions (sine, cosine, arctangent), and more. It supports customizable hardware design parameters, such as precision (16, 32, 64, and 128 bits) and pipeline depths, offering users enhanced flexibility and productivity. The generated code is in an industry-standard hardware description language, ensuring compatibility with standard design flows, including simulation, verification, synthesis, and implementation on both field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).
The Abisko project aims to develop an energy-efficient spiking neural network (SNN) computing architecture and software system capable of autonomous learning and operation. The SNN architecture explores novel neuromorphic devices that are based on resistive-switching materials, such as memristors and electrochemical RAM. Equally important, Abisko uses a deep codesign approach to pursue this goal by engaging experts from across the entire range of disciplines: materials, devices and circuits, architectures and integration, software, and algorithms. Here, the key objectives of our Abisko project are threefold. First, we are designing an energy-optimized high-performance neuromorphic accelerator based on SNNs. This architecture is being designed as a chiplet that can be deployed in contemporary computer architectures and we are investigating novel neuromorphic materials to improve its design. Second, we are concurrently developing a productive software stack for the neuromorphic accelerator that will also be portable to other architectures, such as field-programmable gate arrays and GPUs. Third, we are creating a new deep codesign methodology and framework for developing clear interfaces, requirements, and metrics between each level of abstraction to enable the system design to be explored and implemented interchangeably with execution, measurement, a model, or simulation. As a motivating application for this codesign effort, we target the use of SNNs for an analog event detector for a high-energy physics sensor.
Real-time analysis of patient data during medical procedures can provide vital diagnostic feedback that significantly improves chances of success. With sensors becoming increasingly fast, frameworks such as Deep Neural Networks are required to perform calculations within the strict timing constraints for real-time operation. However, traditional computing platforms responsible for running these algorithms incur a large overhead due to communication protocols, memory accesses, and static (often generic) architectures. In this work, we implement a low-latency Multi-Layer Perceptron (MLP) processor using Field Programmable Gate Arrays (FPGAs). Unlike CPUs and Graphics Processing Units (GPUs), our FPGA-based design can directly interface sensors, storage devices, display devices and even actuators, thus reducing the delays of data movement between ports and compute pipelines. Moreover, the compute pipelines themselves are tailored specifically to the application, improving resource utilization and reducing idle cycles. We demonstrate the effectiveness of our approach using mass-spectrometry data sets for real-time cancer detection. We demonstrate that correct parameter sizing, based on the application, can reduce latency by 20% on average. Furthermore, we show that in an application with tightly coupled data-path and latency constraints, having a large amount of computing resources can actually reduce performance. Using mass-spectrometry benchmarks, we show that our proposed FPGA design outperforms both CPU and GPU implementations, with an average speedup of 144x and 21x, respectively. In our work, we demonstrate the importance of application-specific optimizations in order to minimize latency and maximize resource utilization for MLP inference. By directly interfacing and processing sensor data with ultra-low latency, FPGAs can perform real-time analysis during procedures and provide diagnostic feedback that can be critical to achieving higher percentages of successful patient outcomes.
The Lightwave Energy-Efficient Datacenter (LEED) project within the ARPA-e ENLITENED program is developing novel energy-efficient multichannel lightwave networks. These networks are enabled by a new optical “rotor” switch that can reconfigure the network topology in less than 20 µs and a field-programmable-gate-array-based network interface controller called Corundum that can provide precise network-wide synchronization of packets admitted into the lightwave network. Here we review the optical networking research within LEED and discuss future directions.
The MicroBooNE Continuous Readout Stream is a parallel readout of the MicroBooNE liquid argon time projection chamber (LArTPC) which enables detection of non-beam events such as those from a supernova neutrino burst. The low energies of these neutrinos and the intense cosmic-ray flux due to the near-surface detector location makes triggering on these events very challenging. Instead, MicroBooNE has pioneered a novel approach for detecting supernova neutrinos relying on a delayed trigger generated by SNEWS (the Supernova Early Warning System). The continuous readout of the LArTPC is achieved through the use of real-time compression algorithms (zero suppression and Huffman compression) implemented in an FPGA (field-programmable gate array) in the readout electronics. We present the results of the optimization of the data reduction algorithms, and their operational performance. In order to demonstrate the capability of the continuous stream to detect low-energy electrons, a sample of Michel electrons from stopping cosmic-ray muons is reconstructed and compared to a similar sample from the lossless triggered readout stream.
Field-programmable gate arrays (FPGAs) are becoming more promising for high performance computing (HPC). Unlike fixed hardware specialization, reconfigurability allows FPGAs to be customized for a wide variety of HPC workloads. Our ultimate goal is to understand the viability of FPGAs as accelerators for some of the key HPC codes at LLNL and identify application characteristics that can benefit from the reconfigurability of FPGAs. More specifically, this LDRD project conducted a detailed performance study of FPGAs using sparse matrix computations and identified key optimization techniques to effectively use FPGA hardware resources.
The nucleons - protons and neutrons - are the basic building blocks of atomic nuclei. We now know that the nucleon consists of fundamental particles called quarks and gluons. The quarks interact with each other by exchanging gluons via the strong interaction. Understanding the quark-gluon structure of the nucleon, especially the confinement of quarks within the nucleon in its ground state, remains one of the main unsolved puzzles of particle physics. The nucleon electromagnetic form factors are directly related to the internal structure of the nucleon. A new generation of high precision experiments, GEp-V, GEn-II, GEn-RP, and GMn, measuring the ground state nucleon space-like electro-magnetic form factor at high momentum transfer is underway at Jefferson Lab experimental Hall-A as part of the Super Bigbite Spectrometer (SBS) program. This series of experiments will provide a new level of understanding of the nucleon structure. These experiments are highly demanding due to the extremely fast drop off of the elastic cross section with the increasing four-momentum transfer squared(Q2). This thesis provides an overview of the SBS physics program and reports on the extensive R&D program carried out to achieve the high rate running conditions essential for carrying out the SBS experiments. SBS will provide an intermediate solid angle of approximately 35 msr, which is significantly larger than the solid angle of other dipole based spectrometers at Jefferson lab. Of course, there are much larger acceptance spectrometers at Jefferson Lab, CLAS12 for example. What is special about SBS is that it provides a sizable acceptance while operating at the highest possible luminosity at Jefferson Lab. With this combination of medium acceptance and the highest available luminosity, SBS provides an unparalleled opportunity to explore the nucleon in its ground state with unprecedented resolution. The relatively large acceptance of SBS is achieved by using a large gap dipole magnet and placing it close to the target. An unavoidable consequence of this is that the SBS GEM trackers and other detectors have a clear line-of-sight view of the target and a portion of the beam-line. As a result, the background hit rate in the SBS front GEM trackers is expected to be up to 500 kHz/cm2, over the entire active area of 6000 cm2. To the best of our knowledge, this extremely high rate over such a large area is unprecedented in any particle tracking system used anywhere in the world before. Correctly reconstructing the particle tracks of interest in this very high background environment is achieved by using especially adapted high rate techniques at every step of the tracking process: optimizing the GEM module and tracker design at the hardware level, using high bandwidth electronics and real time Field Programmable Gate Array (FPGA) based background suppression techniques at the Data Acquisition (DAQ) level, and developing highly specialized tracking algorithms to pick out the signal hits from among the vast amount of background hits. In order to ensure a smooth start and running of the SBS experiments, it is extremely crucial that these techniques are developed, implemented, and tested under realistic conditions well before the actual start of the SBS experimental program. A detailed Geant4 simulation of the experiment was combined with a digitization package to generate the detector level pseudodata similar to what is expected in the actual experiments. The digitization procedures were calibrated against actual GEM data from cosmic-ray runs, X-ray tests, beam test runs in experimental Hall-A, and the PRad experiment in Hall B. Then, optimized tracking algorithms were developed and implemented in an analysis program used to analyze these pseudo-data and to extract expected high-level parameters. These extracted quantities were then compared with the input parameters from the simulation to verify and determine the performance characteristics for the SBS tracker. From this work, a final tracking efficiency of 69% at 25% occupancy was achieved, with the required reconstruction accuracy, for the GMn experiment, the first experiment in the SBS program, with background level at 100 kHz/cm2. These demonstrated parameters are adequate for the successful running of not only the GMn experiment but as well as for GEn-RP and GEn-II experiments, the second and third experiments in the program. This work builds the solid ground to further improve the tracking performance for these experiments and achieve similar conditions for the running of the GEp-V experiment, the most demanding experiment in the SBS program, with an expected background level at 500 kHz/cm2.
UC Davis has fabricated an ultrashort pulse reflectometer (USPR) diagnostic instrument for electron density profile measurements on compact, short duration, magnetically-confined fusion-energy concept devices such as spheromaks and FRCs. The USPR system transmits extremely short duration (~few nsec) chirped waveforms that together span 29 to 75 GHz. These chirped waveforms illuminate and reflect from the target plasma, with each frequency component reflecting from a different density layer (higher frequencies probe deeper into the plasma before reflecting). The reflected waveforms are split into roughly 42 different frequencies; time-of-flight (TOF) measurements made at each frequency with high resolution (~25 psec measurement resolution which corresponds to ~5 mm). These TOF data may then be inverted via software to generate electron density profiles with high time resolution (~10 μsec). At the heart of the system is a field programmable gate array (FPGA) based controller which collects and processes all of the USPR data in addition to generating all of the control signals required for maximum flexibility. The FPGA controller has the software flexibility to be easily reconfigured for different plasma devices, and the entire system sufficiently compact to be easily and quickly transported between devices. A high speed impulse generator was transformed into a set of three ultrashort pulse transmitter chirps using a combination of dispersive waveguide, frequency doublers and high-pass filters. A mm-wave controller was fabricated to sequentially switch between the three chirps, directing the chirps one-by-one to three different mm-wave assemblies spanning 29-75 GHz. Each mm-wave assembly consists of a high power active multiplier chain which converts the transmitter chirp to higher frequencies, and a broadband mixer which downconverts the reflected waveform to the 2-18 GHz range of the UPSR receiver. The 16-channel receiver (shared by all 3 mm-wave assemblies) was fabricated employing custom TOF modules capable of operating at a high 1 MHz sampling rate. Laboratory testing of the full system revealed the presence of unwanted harmonics from the multiplication process, with interference observed in the downconverted reflections at selected frequency channels that could not be completely filtered out. Additional interference effects arising from internal reflections within the mm-wave assemblies were minimized using a high-speed switch which served to “gate out” much of these reflections. The USPR diagnostic was transported and installed onto the HIT-SIU plasma device, becoming operational on 11/08/2022. Although designed to span 3 distinct mm-wave bands, the HIT-SIU plasmas at this time were sufficiently low density such that only the lowest of the three bands was likely to have strong plasma reflections. The system was then set to operate on only the lowest band (assembly #1), with data collected every 1 μsec rather than 3 μsec which would have been the case when cycling through all three bands. Connected to HIT-SIU, time-varying plasma reflections were observed on 9 of 16 possible frequency channels. Close examination of the data collected revealed issues previously unobserved in laboratory testing, associated with (a) reflections from the small aperture horns required for operation within the HIT-SIU device, and (b) a dependence of the recorded TOF with the threshold voltage of a given channel. Plans were made to address each of these issues before undertaking any future campaigns.
The objective of the project is to demonstrate that critical control functions can be implemented using little resources in modern microelectronics. A finite state machine (Figure 1) is implemented onto a field programmable gate array (FPGA). The functionality of the system is demonstrated by sending binary instructions to the controller. The controller transmits patterns through an LED, controls an electromechanical device, and uses pulse-width modulation (PWM) for radar functions.
Recently, a new graph Laplacian, called the inner product Laplacian, was introduced which generalizes many existing Laplacians, including the normalized and combinatorial Laplacian and their weighted variants. The key observation behind the inner product Laplacian is that by defining appropriate inner product spaces on the vertices and edges, the standard Laplacians can be recovered as Hodge Laplacians over the simplicial complex formed by the edges and vertices. These inner product spaces form a natural way to incorporate non-combinatorial information into the definition of a domain-specific Laplacian. In particular, in contrast to current domain-specific weighting schemes which rely solely on edge weights, information regarding the similarity of non-adjacent vertices and arbitrary pairs of edges can be effectively incorporated into the Laplacian. In order to illustrate this approach we consider the problem of calculating the potential energy of an atomistic configuration using Graph Neural Networks. In comparison with start-of-the-art approaches, such as SchNet, our approach replaces a learned (via auto-encoder) representation of the atom types with an inner product space on atoms based on scientific knowledge (e.g., electronegativity). We will illustrate how this approach captures key chemical properties of the molecules and compare the energy calculations with state-of-the-art neural network approaches. However, to compute the resulting Laplacian involves a mixture of sparse and dense matrix computation and yields a dense matrix as the basis for the graph convolution. This dense convolutional kernel necessitates moving away from the standard message passing framework for graph neural networks and increases the computational cost of applying the kernel. In order to mitigate these costs we investigate means of leveraging the mixed sparse and dense computations to reduce the overall computational cost and how these approaches can be automatically transferred to energy efficient hardware (e.g., field programmable gate arrays (FPGAs)).
The goal of this project is to implement real-time analysis of 2D Beam Emission Spectroscopy (BES) data to predict and control transient and high-bandwidth events at DIII-D. In essence, we wish to bring high-bandwidth fluctuation diagnostics into the realm of real-time measurements and control. The BES ML models will necessarily be deep neural networks (DNN) with a “data flow” architecture for compatibility with high-throughput, low-latency evaluation on a field-programmable gate array (FPGA) or other emerging processor technologies. The real-time output will be fed to the plasma control system (PCS) for real-time control tasks, specifically for ELM control and avoidance and for QH-mode access and sustainment. We anticipate that the real-time analysis of fluctuation diagnostics will create new enabling technologies to predict and control transient events such as confinement mode transitions, edge-localized modes, Alfven eigenmode events, and disruptions. The proposed research is aligned with ITER research needs and DIII-D programmatic goals. For instance, the prediction and avoidance of ELM events is critical for ITER machine safety. Also, H-mode access with RMP ELM suppression in ITER is an active research area due to high separatrix density, narrow SOL width, and elevated LH transition power threshold.
This project was motivated by State-of-the-Art (SOTA) technology that incorporates Network on Chips (NOC) for efficient data communication across the various computer kernels. For example, on the AMD Versal Field Programmable Gate Arrays (FPGA), an NoC has been incorporated for fast data communication from the programmable logic and other computer kernels (processing system, adaptable intelligence engines, etc.). The radiation effects on the legacy technology of this FPGA, such as the programmable logic, are well understood, and established methods exist to measure cross-sections when new families/generations are released; however, newly incorporated technologies, such as the NoC, are not fully understood and could introduce new failure points into the mission space.
The overall vision of this project was to integrate real-time artificial intelligence (AI) directly into the data acquisition and detector-control systems of nuclear physics experiments, including both fast online event selection and an autonomous detector-control feedback loop. The work carried out under the award focused on the fast online event-selection half of that vision: the efficient recording of low-momentum heavy-flavor (HF) hadron decays in proton-proton collisions at the sPHENIX experiment at the Relativistic Heavy Ion Collider (RHIC)—an observable that requires fast tracking and topological trigger selection not previously demonstrated at RHIC, and that is essential for QCD studies at future facilities such as the Electron-Ion Collider (EIC). The autonomous detector-control (GPU-based feedback) component named in the project title remained a design concept and was not implemented under this award. The Massachusetts Institute of Technology (MIT) group led the offline simulation and data processing needed to train the machine-learning (ML) models, the translation of trained models to Field-Programmable Gate Array (FPGA) firmware using the hls4ml framework, and the physics validation of heavy-flavor reconstruction. Over the award period, the team developed and hardware-tested the principal components of an AI-based heavy-flavor trigger on simulated and recorded sPHENIX tracker data: a software Bipartite Graph Attention Network (BiGAT) trigger model reaching > 95% signal efficiency at 99% background rejection; an FPGA-native hit clusterizer matching the offline clustering; smaller networks synthesized to FPGA within the required sub-10 µs latency; and an assembled decoder–clusterizer–inference firmware chain exercised on the FELIX readout board. A complete, fully integrated hardware demonstrator was not finished within the award period. This report documents the project goals, the MIT group’s contributions, the technical accomplishments, and the outlook toward applications at the future EIC ePIC detector.