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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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On-Chip p-MOSFET Dosimetry
On-chip p-FETs were developed to monitor the radiation dose of n-well CMOS ICs by monitoring threshold voltage shifts due to radiation induced oxide and interface charge.
Single-Event Effect Testing of the Cree CMF10120D SiC Power MOSFET
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RF simulation of self-aligned T-shape S/D contact InAs MOSFET on silicon
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Effects of Incident Angle on Single-Event Leakage Current Degradation in Heavy-Ion Irradiated 1800 V and 4500 V SiC Power MOSFETs
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Electro-thermal Simulation and Performance Comparison of 1.2 kV 10 A Vertical GaN MOSFETs.
Abstract not provided.
3.3-kV SiC MOSFET Performance and Channel-Length Related Short-Circuit Capability.
Abstract not provided.
Electro-thermal Simulation and Performance Comparison of 1.2 kV 10 A Vertical GaN MOSFETs.
Abstract not provided.
Total Ionizing Dose Effect Study on Radiation-Hard Power MOSFET Device.
Abstract not provided.
Automotive-Qualified 3300 V SiC MOSFETs for next-generation extreme fast chargers
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Power MOSFET and JBSFET cell topologies with superior high frequency figure of merit
A vertical insulated-gate field effect transistor includes a semiconductor substrate and a gate electrode on a first surface thereof. This gate electrode has a plurality of eight (or more) sided openings extending therethrough. Each of these openings has eight (or more) sidewalls, including a first plurality of sidewalls that are flat relative to a center of the opening and second plurality of sidewalls that are either flat or concave relative to the center of the opening. A source electrode is also provided, which extends into the openings. This source electrode may ohmically contact a source region within the semiconductor substrate. If the field effect transistor is a JBSFET, the source electrode may also form a Schottky rectifying junction with a drift region within the semiconductor substrate.
Understanding the Initial Stages of Time Dependent Dielectric Breakdown in Si/SiO2 MOSFETs Utilizing EDMR and NZFMR.
Abstract not provided.
Advanced Power Conversion Systems featuring SiC MOSFETs with In-Situ Restoration Capabilities
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Total Ionizing Dose Effects on Gallium Oxide MOSFETs
This summary will be submitted for review for the 2025 HEART conference.
DC Cryogenic Modeling of Open-Source SkyWater 130 nm MOSFETs at 77 K Using BSIM4
Cryogenic applications in high-energy physics (HEP) demand reliable, low-power CMOS electronics capable of operating at liquid nitrogen temperatures (77 K). The open-source SkyWater 130nm (SKY130) CMOS process has previously been shown to operate at temperatures as low as 4 K making it a promising candidate for HEP applications. In this work, we characterize and model SKY130 low-threshold voltage transistors at 77 K, which is a temperature commonly used in modeling applications for liquid argon detectors. DC characteristic measurements were performed at both room temperature and liquid nitrogen temperature. We created a cryogenic modeling approach to produce a SPICE-compatible, isothermal BSIM4-based model for select transistor sizes at 77 K. The resulting model agrees with data at 77 K with an average error on the order of 20% (relative RMS) and shows no dependence on drain voltage. Due to the open-source nature of SKY130, we have made our models publicly available on Github. We hope this work will continue the trend for democratizing circuit design at cryogenic temperatures in high-energy physics by enabling open access to accurate cryogenic CMOS device models at 77 K.
Investigation of the Semicoa 2N7616 and 2N7425 and the Microsemi 2N7480 for Single-Event Gate Rupture and Single-Event Burnout
Single-event-effect test results for hi-rel total-dose-hardened power MOSFETs are presented in this report. The 2N7616 and the 2N7425 from Semicoa and the 2N7480 from International Rectifier were tested to NASA test condition standards and requirements. The 2N7480 performed well and the data agree with the manufacture's data. The 2N7616 and 2N7425 were entry parts from Semicoa using a new device architecture. Unfortunately, the device performed poorly and Semicoa is withdrawing power MOSFETs from it line due to these data. Vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) are the most commonly used power transistor. MOSFETs are typically employed in power supplies and high current switching applications. Due to the inherent high electric fields in the device, power MOSFETs are sensitive to heavy ion irradiation and can fail catastrophically as a result of single-event gate rupture (SEGR) or single-event burnout (SEB). Manufacturers have designed radiation-hardened power MOSFETs for space applications. See [1] through [5] for more information. The objective of this effort was to investigate the SEGR and SEB responses of two power MOSFETs recently produced. These tests will serve as a limited verification of these parts. It is acknowledged that further testing on the respective parts may be needed for some mission profiles.
CRRES microelectronic test chip
The JPL CRRES chip was designed and fabricated in 1985 and included in the CRRES MEP. MOSFET Matrix results show the effect of shielding on radiation-induced MOSFET threshold voltage shifts and channel mobility degradation. Shielded (middle board) MOSFETs have a threshold-voltage damage factor that is approximately three orders of magnitude smaller than would be estimated from Co-60 ground tests. Unshielded (outer board) MOSFETs have a threshold-voltage damage factor that would be estimated from Co-60 ground tests. Temperature swings as large as 23 C with a 22.5 orbit periodicity affected the MOSFET data and were removed from the data in order to reveal the radiation effects. This experiment demonstrated the feasibility of characterizing MOSFETs in a matrix, thus reducing the complexity and mass of the experiment.