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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS2002

Efficient Design in a DC to DC Converter Unit

Space Flight hardware requires high power conversion efficiencies due to limited power availability and weight penalties of cooling systems. The International Space Station (ISS) Electric Power System (EPS) DC-DC Converter Unit (DDCU) power converter is no exception. This paper explores the design methods and tradeoffs that were utilized to accomplish high efficiency in the DDCU. An isolating DC to DC converter was selected for the ISS power system because of requirements for separate primary and secondary grounds and for a well-regulated secondary output voltage derived from a widely varying input voltage. A flyback-current-fed push-pull topology or improved Weinberg circuit was chosen for this converter because of its potential for high efficiency and reliability. To enhance efficiency, a non-dissipative snubber circuit for the very-low-Rds-on Field Effect Transistors (FETs) was utilized, redistributing the energy that could be wasted during the switching cycle of the power FETs. A unique, low-impedance connection system was utilized to improve contact resistance over a bolted connection. For improved consistency in performance and to lower internal wiring inductance and losses a planar bus system is employed. All of these choices contributed to the design of a 6.25 KW regulated dc to dc converter that is 95 percent efficient. The methodology used in the design of this DC to DC Converter Unit may be directly applicable to other systems that require a conservative approach to efficient power conversion and distribution.

Bruemmer, Joel E.↗
NASA NTRS2003

Single Event Effects Testing of the Linfinity SG1525A Pulse Width Modulator Controller

Pulse Width Modulator (PWM) Controllers are the heart of switching power supply systems in development today. The PWMs considered here have the same integration advantages as many other controllers but it also includes the interface drivers for the follow-on power Field Effect Transistors (FET). Previous work on these types of devices looked into the required test methodologies [ 11 and the impact of radiation on the soft start and shutdown circuits of typically incorporated in the technology [2]. Taking advantage of this previous work this study was undertaken to determine the single event destructive and transient susceptibility of the Linfinity SG1525A Pulse Width Modulator Controller. The device was monitored for transient interruptions in the output signals and for destructive events induced by exposing it to a heavy ion beam at the Texas A&M University Cyclotron Single Event Effects Test Facility. After exposing these devices to the beam, a new upset mode has been identified that can lead to catastrophic power supply system failure if this event would occur while drive power FETs off the two device outputs. The devices and the test methods used will be described first. This will be followed by a brief description of the data collected to date (not all data can be presented with the length constraints of the summary) and a summary of the key results.

Howard, J. W., Jr.↗
NASA NTRS2003

Electrospun Polyaniline/Polyethylene Oxide Nanofiber Field Effect Transistor

We report on the observation of field effect transistor (FET) behavior in electrospun camphorsulfonic acid doped polyaniline(PANi)/polyethylene oxide(PE0) nanofibers. Saturation channel currents are observed at surprisingly low source/drain voltages. The hole mobility in the depletion regime is 1.4 x 10(exp -4) sq cm/V s while the 1-D charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating 1-D polymer FET's.

Pinto, N. J.↗
NASA NTRS2004

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Demonstrated

Novel transistors and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low-power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. For NASA applications, nanotechnology offers tremendous opportunities for increased onboard data processing, and thus autonomous decisionmaking ability, and novel sensors that detect and respond to environmental stimuli with little oversight requirements. Polyaniline/polyethylene oxide (PANi/PEO) nanofibers are of interest because they have electrical conductivities that can be changed from insulating to metallic by varying the doping levels and conformations of the polymer chain. At the NASA Glenn Research Center, we have observed field effect transistor (FET) behavior in electrospun PANi/PEO nanofibers doped with camphorsulfonic acid. The nanofibers were deposited onto Au electrodes, which had been prepatterned onto oxidized silicon substrates. The preceding scanning electron image shows the device used in the transistor measurements. Saturation channel currents are observed at surprisingly low source/drain voltages (see the following graph). The hole mobility in the depletion regime is 1.4x10(exp -4)sq cm/V sec, whereas the one-dimensional charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx.10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating one-dimensional polymer FET's.

Mueller, Carl H.↗
NASA NTRS2005

Temperature Tolerant Evolvable Systems Utilizing FPGA Boards and Bias-Controlled Amplifiers

Space missions often require radiation and extreme-temperature hardened electronics to survive the harsh environments beyond Earth's atmosphere. Traditional approaches to preserve electronics incorporate shielding, insulation and redundancy at the expense of power and weight. However, a novel way of bypassing these problems is the concept of evolutionary hardware. A reconfigurable device, consisting of several switches interconnected with analog/digital parts, is controlled by an evolutionary processor (EP). When the EP detects degradation in the circuit it sends signals to reconfigure the switches, thus forming a new circuit with the desired output. This concept has been developed since the mid-l990s, but one problem remains-the EP cannot degrade substantially. For this reason, extensive testing at extreme temperatures (-180 to 120 C) has been done on devices found on FPGA boards (taking the role of the EP), such as the Analog to Digital and the Digital to Analog Converter. The EP is used in conjunction with a bias-controlled amplifier and a new prototype relay board, which is interconnected with 6 G4-FETs, a tri-input transistor-like element developed at JPL. The greatest improvements to be made lie in the reconfigurable device, so future design and testing of the G4-FET chip is required.

Kumar, Nikhil R.↗
NASA NTRS2009

Improved Signal Chains for Readout of CMOS Imagers

An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

Pain, Bedabrata↗
NASA NTRS2007

Multiloop Rapid-Rise/Rapid Fall High-Voltage Power Supply

A proposed multiloop power supply would generate a potential as high as 1.25 kV with rise and fall times <100 s. This power supply would, moreover, be programmable to generate output potentials from 20 to 1,250 V and would be capable of supplying a current of at least 300 A at 1,250 V. This power supply is intended to be a means of electronic shuttering of a microchannel plate that would be used to intensify the output of a charge-coupled-device imager to obtain exposure times as short as 1 ms. The basic design of this power supply could also be adapted to other applications in which high voltages and high slew rates are needed. At the time of reporting the information for this article, there was no commercially available power supply capable of satisfying the stated combination of voltage, rise-time, and fall-time requirements. The power supply would include a preregulator that would be used to program a voltage 1/30 of the desired output voltage. By means of a circuit that would include a pulse-width modulator (PWM), two voltage doublers, and a transformer having two primary and two secondary windings, the preregulator output voltage would be amplified by a factor of 30. A resistor would limit the current by controlling a drive voltage applied to field-effect transistors (FETs) during turn-on of the PWM. Two feedback loops would be used to regulate the high output voltage. A pulse transformer would be used to turn on four FETs to short-circuit output capacitors when the outputs of the PWM were disabled. Application of a 0-to-5-V square to a PWM shut-down pin would cause a 20-to-1,250-V square wave to appear at the output.

Bearden, Douglas↗
NASA NTRS2007

Using G4FETs as a Data Router for In-Plane Crossing of Signal Paths

Theoretical analysis and some experiments have demonstrated that siliconon- insulator (SOI) 4-gate transistors the type known as G(exp 4)FETs could be efficiently used for in-plane crossing of signal paths. Much of the effort of designing very-large-scale integrated (VLSI) circuits is focused on area-efficient routing of signals. The main source of difficulty in VLSI signal routing is the requirement to prevent crossing, in the same plane, of wires that are meant to be kept electrically insulated from each other. Consequently, it often becomes necessary to design and build VLSI circuits in multiple layers with vias (connections between conductors in different layers at selected locations). Suitable devices that would prevent, or at least sufficiently suppress, undesired electrical coupling (cross-talk) between wires crossing in the same plane would enable compact, simpler implementation complex interconnection networks with in-plane crossings that, heretofore, have not been possible in VLSI circuitry. The use of G4FETs as in-plane signal-crossing devices or routers, in combination with the use of G(exp 4)FETs as universal programmable logic gates, would create opportunities for reducing complexity in VLSI design.

Fijany, Amir↗
NASA NTRS2007

High-Voltage Power Supply With Fast Rise and Fall Times

A special-purpose high-voltage power supply can be electronically switched on and off with fast rise and fall times, respectively. The output potential is programmable from 20 to 1,250 V. An output current of 50 A can be sustained at 1,250 V. The power supply was designed specifically for electronically shuttering a microchannel plate in an x-ray detector that must operate with exposure times as short as 1 ms. The basic design of the power supply is also adaptable to other applications in which there are requirements for rapid slewing of high voltages. The power-supply circuitry (see figure) includes a preregulator, which is used to program the output at 1/30 of the desired output potential. After the desired voltage has been set, the outputs of a pulse width modulator (PWM) are enabled and used to amplify the preregulator output potential by 30. The amplification is achieved by use of two voltage doublers with a transformer that has two primary and two secondary windings. A resistor is used to limit the current by controlling the drive voltage of two field-effect transistors (FETs) during turn-on of the PWM. A pulse transformer is used to turn on four FETs to short-circuit four output capacitors when the outputs of the PWM have been disabled. The most notable aspects of the performance of the power supply are a rise time of only 80 s and a fall time of only 60 s at a load current of 50 A or less. Another notable aspect is that the application of a 0-to-5-V square wave to a shutdown pin of the PWM causes the production of a 0-to-1,250-V square wave at the output terminals.

Bearden, Douglas B.↗
NASA NTRS2006

Single-Chip T/R Module for 1.2 GHz

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Moussessian, Alina↗
NASA NTRS2013

Fully Printed, Flexible, Phased Array Antenna for Lunar Surface Communication

NASAs future exploration missions focus on the manned exploration of the Moon, Mars, and beyond, which will rely heavily on the development of a reliable communications infrastructure from planetary surface-to-surface, surface-to-orbit, and back to Earth. Flexible antennas are highly desired in many scenarios. Active phased array antennas (active PAAs) with distributed control and processing electronics at the surface of an antenna aperture offer numerous advantages for radar communications. Large-area active PAAs on flexible substrates are of particular interest in NASA s space radars due to their efficient inflatable package that can be rolled up during transportation and deployed in space. Such an inflatable package significantly reduces stowage volume and mass. Because of these performance and packaging advantages, large-area inflatable active PAAs are highly desired in NASA s surface-to-orbit and surface-to-relay communications. To address the issues of flexible electronics, a room-temperature printing process of active phased-array antennas on a flexible Kapton substrate was developed. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proved feasible for the PAA system. This innovation is a new type of fully inkjet-printable, two-dimensional, high-frequency PAA on a flexible substrate at room temperature. The designed electronic circuit components, such as the FET switches in the phase shifter, metal interconnection lines, microstrip transmission lines, etc., are all printed using a special inkjet printer. Using the developed technology, entire 1x4, 2x2, and 4x4 PAA systems were developed, packaged, and demonstrated at 5.3 GHz. Several key solutions are addressed in this work to solve the fabrication issues. The source/drain contact is developed using droplets of silver ink printed on the source/drain areas prior to applying CNT thin-film. The wet silver ink droplets allow the silver to wet the CNT thin-film area and enable good contact with the source and drain contact after annealing. A passivation layer to protect the device channel is developed by bonding a thin Kapton film on top of the device channel. This film is also used as the media for transferring the aligned CNT thin-film on the device substrate. A simple and cost-effective technique to form multilayer metal interconnections on flexible substrate is developed and demonstrated. Contact vias are formed on the second substrate prior to bonding on the first substrate. Inkjet printing is used to fill the silver ink into the via structure. The printed silver ink penetrates through the vias to contact with the contact pads on the bottom layer. It is then annealed to form a good connection. One-dimensional and two-dimensional PAAs were fabricated and characterized. In these circuits, multilayer metal interconnects were used to make a complete PAA system.

Subbaraman, Harish↗
DOE OSTI2020

Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

42 ENGINEERING↗
DOE OSTI2023

Magnetoelectric XNOR logic gate device

A magneto-electric (ME) XNOR logic gate device includes a conducting device; and a ME-FET coupled to the conducting device. The ME-FET can be formed of a split gate; a first gate terminal coupled to a first portion of the split gate for receiving a first input signal; a second gate terminal coupled to a second portion of the split gate for receiving a second input signal; a source terminal coupled to a ground line; and a drain terminal coupled to the conducting device.

Gaul, Nishtha Sharma↗
NASA NTRS1993

On-Chip p-MOSFET Dosimetry

On-chip p-FETs were developed to monitor the radiation dose of n-well CMOS ICs by monitoring the threshold voltage shifts due to radiation induced oxide and interface charge.

FET's↗
NASA NTRS1993

On-Chip p-MOSFET Dosimetry

On-chip p-FETs were developed to monitor the radiation dose of n-well CMOS ICs by monitoring threshold voltage shifts due to radiation induced oxide and interface charge.

FETs↗
DOE OSTI2024

Low Resistance Contact to P-Type Monolayer WSe 2

Advanced microelectronics in the future may require semiconducting channel materials beyond silicon. Two-dimensional (2D) semiconductors, with their atomically thin thickness, hold great promise for future electronic devices. One challenge to achieving high-performance 2D semiconductor field effect transistors (FET) is the high contact resistance at the metal-semiconductor interface. Here, in this study, we develop a charge-transfer doping strategy with WSe 2 /α-RuCl 3 heterostructures to achieve low-resistance ohmic contact for p-type monolayer WSe2 transistors. We show that hole doping as high as 3 × 10 13 cm -2 can be achieved in the WSe 2 /α-RuCl 3 heterostructure due to its type-III band alignment, resulting in an ohmic contact with resistance of 4 kΩ μm. Based on that, we demonstrate p-type WSe 2 transistors with an on-current of 35 μA·μm -1 and an I ON /I OFF ratio exceeding 10 9 at room temperature.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Rapid, Sensitive, Label-Free Electrical Detection of SARS-CoV-2 in Nasal Swab Samples

Rapid diagnosis of coronavirus disease 2019 (COVID-19) is key for the long-term control of severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) amid renewed threats of mutated SARS-CoV-2 around the world. Here, we report on an electrical label-free detection of SARS-CoV-2 in nasopharyngeal swab samples directly collected from outpatients or in saliva-relevant conditions by using a remote floating-gate field-effect transistor (RFGFET) with a 2-dimensional reduced graphene oxide (rGO) sensing membrane. RFGFET sensors demonstrate rapid detection (<5 min), a 90.6% accuracy from 8 nasal swab samples measured by 4 different devices for each sample, and a coefficient of variation (CV) < 6%. Also, RFGFET sensors display a limit of detection (LOD) of pseudo-SARS-CoV-2 that is 10 000-fold lower than enzyme-linked immunosorbent assays, with a comparable LOD to that of reverse transcriptionpolymerase chain reaction (RT-PCR) for patient samples. To achieve this, comprehensive systematic studies were performed regarding interactions between SARS-CoV-2 and spike proteins, neutralizing antibodies, and angiotensin-converting enzyme 2, as either a biomarker (detection target) or a sensing probe (receptor) functionalized on the rGO sensing membrane. Finally, taken together, this work may have an immense effect on positioning FET bioelectronics for rapid SARS-CoV-2 diagnostics.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2021

First demonstration of robust tri-gate β-Ga 2 O 3 nano-membrane field-effect transistors

Nano-membrane tri-gate β-gallium oxide (β-Ga 2 O 3 ) field-effect transistors (FETs) on SiO 2 /Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with the footprint channel width of 50 nm. For high-quality interface between β-Ga 2 O 3 and gate dielectric, atomic layer-deposited 15 nm thick aluminum oxide (Al 2 O 3 ) was utilized with tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV dec –1 , high drain current (I DS ) ON/OFF ratio of 1.5 × 10 9 , and negligible transfer characteristic hysteresis. Furthermore, we also experimentally demonstrated robustness of these devices with current–voltage (I–V) characteristics measured at temperatures up to 400 °C.

77 NANOSCIENCE AND NANOTECHNOLOGY↗