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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Optical techniques to feed and control GaAs MMIC modules for phased array antenna applications

A complex signal distribution system is required to feed and control GaAs monolithic microwave integrated circuits (MMICs) for phased array antenna applications above 20 GHz. Each MMIC module will require one or more RF lines, one or more bias voltage lines, and digital lines to provide a minimum of 10 bits of combined phase and gain control information. In a closely spaced array, the routing of these multiple lines presents difficult topology problems as well as a high probability of signal interference. To overcome GaAs MMIC phased array signal distribution problems optical fibers interconnected to monolithically integrated optical components with GaAs MMIC array elements are proposed as a solution. System architecture considerations using optical fibers are described. The analog and digital optical links to respectively feed and control MMIC elements are analyzed. It is concluded that a fiber optic network will reduce weight and complexity, and increase reliability and performance, but higher power will be required.

Bhasin, K. B.↗
NASA NTRS1970

Color television system using single gun color cathode ray tube

Two-primary color and single gun system provides quality differential color and variation in brightness for specific colors by varying current and controlling duty cycle of electron beam. Number of video amplifiers, deflection circuits, and guns required to display color TV picture is reduced and less complex tube is required.

Gaiser, E. E.↗
NASA NTRS1971

Automatic transmission line monitor

Monitor improves complex network reliability in computer data links and command transmission lines. System evaluates circuit performance against preselected criteria, identifies and stores data indicating out-of-tolerance conditions, conducts closed loop testing, and provides for operation under command of digital computer that determines restoration priorities.

Parsons, W. E.↗
NASA NTRS1980

Development of Boolean calculus and its applications

The development of Boolean calculus for its application to developing digital system design methodologies that would reduce system complexity, size, cost, speed, power requirements, etc., is discussed. Synthesis procedures for logic circuits are examined particularly asynchronous circuits using clock triggered flip flops.

Tapia, M. A.↗
NASA NTRS2003

Measured Propagation Characteristics of Coplanar Waveguide on Semi-Insulating 4H-SiC Through 800 K

Wireless sensors for high temperature industrial applications and jet engines require RF transmission lines and RF integrated circuits (RFICs) on wide bandgap semiconductors such as SiC. In this paper, the complex propagation constant of coplanar waveguide fabricated on semiinsulating 4H-SiC has been measured through 813 K. It is shown that the attenuation increases 3.4 dB/cm at 50 GHz as the SiC temperature is increased from 300 K to 813 K. Above 500 K, the major contribution to loss is the decrease in SiC resistivity. The effective permittivity of the same line increases by approximately 5 percent at microwave frequencies and 20 percent at 1 GHz.

Ponchak, George E.↗
NASA NTRS2017

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Today's launch vehicles complex electronic and avionics systems heavily utilize Field Programmable Gate Array (FPGA) integrated circuits (IC) for their superb speed and reconfiguration capabilities. Consequently, FPGAs are prevalent ICs in communication protocols such as MILSTD- 1553B and in control signal commands such as in solenoid valve actuations. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Al Hassan, Mohammad↗
NASA NTRS2013

An Efficient Model-based Diagnosis Engine for Hybrid Systems Using Structural Model Decomposition

Complex hybrid systems are present in a large range of engineering applications, like mechanical systems, electrical circuits, or embedded computation systems. The behavior of these systems is made up of continuous and discrete event dynamics that increase the difficulties for accurate and timely online fault diagnosis. The Hybrid Diagnosis Engine (HyDE) offers flexibility to the diagnosis application designer to choose the modeling paradigm and the reasoning algorithms. The HyDE architecture supports the use of multiple modeling paradigms at the component and system level. However, HyDE faces some problems regarding performance in terms of complexity and time. Our focus in this paper is on developing efficient model-based methodologies for online fault diagnosis in complex hybrid systems. To do this, we propose a diagnosis framework where structural model decomposition is integrated within the HyDE diagnosis framework to reduce the computational complexity associated with the fault diagnosis of hybrid systems. As a case study, we apply our approach to a diagnostic testbed, the Advanced Diagnostics and Prognostics Testbed (ADAPT), using real data.

Structural Decomposition↗
NASA NTRS1993

Faulty behavior of asynchronous storage elements

It is often assumed that the faults in storage elements (SE's) can be modeled as output/input stuck-at-faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. A more accurate higher level fault model for elementary SE's used in asynchronous circuits is presented. This model offers better representation of the physical failures. It is shown that the stuck-at model may be adequate if only modest fault coverage is desired. The enhanced model includes some common fault behaviors of SE's that are not covered by the stuck-at model. These include data-feed-through behaviors that cause the SE to be combinational. Fault models for complex SE cells can be obtained without a significant loss of information about the structure of the circuit.

Al-Assadi, Waleed K.↗
NASA NTRS1997

Validation of an Accurate Three-Dimensional Helical Slow-Wave Circuit Model

The helical slow-wave circuit embodies a helical coil of rectangular tape supported in a metal barrel by dielectric support rods. Although the helix slow-wave circuit remains the mainstay of the traveling-wave tube (TWT) industry because of its exceptionally wide bandwidth, a full helical circuit, without significant dimensional approximations, has not been successfully modeled until now. Numerous attempts have been made to analyze the helical slow-wave circuit so that the performance could be accurately predicted without actually building it, but because of its complex geometry, many geometrical approximations became necessary rendering the previous models inaccurate. In the course of this research it has been demonstrated that using the simulation code, MAFIA, the helical structure can be modeled with actual tape width and thickness, dielectric support rod geometry and materials. To demonstrate the accuracy of the MAFIA model, the cold-test parameters including dispersion, on-axis interaction impedance and attenuation have been calculated for several helical TWT slow-wave circuits with a variety of support rod geometries including rectangular and T-shaped rods, as well as various support rod materials including isotropic, anisotropic and partially metal coated dielectrics. Compared with experimentally measured results, the agreement is excellent. With the accuracy of the MAFIA helical model validated, the code was used to investigate several conventional geometric approximations in an attempt to obtain the most computationally efficient model. Several simplifications were made to a standard model including replacing the helical tape with filaments, and replacing rectangular support rods with shapes conforming to the cylindrical coordinate system with effective permittivity. The approximate models are compared with the standard model in terms of cold-test characteristics and computational time. The model was also used to determine the sensitivity of various circuit parameters including typical manufacturing dimensional tolerances and support rod permittivity. By varying the circuit parameters of an accurate model using MAFIA, these sensitivities can be computed for manufacturing concerns, and design optimization previous to fabrication, thus eliminating the need for costly experimental iterations. Several variations were made to a standard helical circuit using MAFIA to investigate the effect that variations on helical tape and support rod width, metallized loading height and support rod permittivity, have on TWT cold-test characteristics.

Kory, Carol L.↗
NASA NTRS1988

A simplified, general-purpose deep-space ranging correlator design

A much-simplified, yet more general-purpose multi-channel deep-space ranging system correlator design that was used in past JPL spacecraft ranging systems is described. The method applies to detection of both single-component and multiple-component ranging codes, in either sequential (mu) or composite (pi) transmitted forms, and using either pseudonoise or square-wave components. Using this design, the Phobos Probe ranging system correlator computational complexity was reduced by over three orders of magnitude in multiply-and-add circuits and 45,000 bits of accumulator storage.

Tausworthe, R. C.↗
NASA NTRS1999

High Temperature Superconductor/Semiconductor Hybrid Microwave Devices and Circuits

Contents include following: film deposition technique; laser ablation; magnetron sputtering; sequential evaporation; microwave substrates; film characterization at microwave frequencies; complex conductivity; magnetic penetration depth; surface impedance; planar single-mode filters; small antennas; antenna arrays phase noise; tunable oscillations; hybrid superconductor/semiconductor receiver front ends; and noise modeling.

Romanofsky, Robert R.↗
NASA NTRS2017

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

Al Hassan, Mohammad↗
NASA NTRS2016

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

JFET↗
NASA NTRS1993

Design and implementation of GaAs HBT circuits with ACME

GaAs HBT circuits offer high performance (5-20 GHz) and radiation hardness (500 Mrad) that is attractive for space applications. ACME is a CAD tool specifically developed for HBT circuits. ACME implements a novel physical schematic-capture design technique where designers simultaneously view the structure and physical organization of a circuit. ACME's design interface is similar to schematic capture; however, unlike conventional schematic capture, designers can directly control the physical placement of both function and interconnect at the schematic level. In addition, ACME provides design-time parasitic extraction, complex wire models, and extensions to Multi-Chip Modules (MCM's). A GaAs HBT gate-array and semi-custom circuits have been developed with ACME; several circuits have been fabricated and found to be fully functional .

Hutchings, Brad L.↗
NASA NTRS1990

Assessing the SEU resistance of CMOS latches using alpha-particle sensitive test circuits

The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environment is evident in the upset rate of the Tracking and Data Relay Satellite (TDRS) launched in Apr. 1983. This satellite experiences a single-event-upset (SEU) per day which must be corrected from the ground. Such experience caused a redesign of the Galileo spacecraft with SEU resistant IC's. The solution to the SEU problem continues to be important as the complexity of spacecraft grows, the feature size of IC's decreases, and as space systems are designed with circuits fabricated at non-radiation hardened foundries. This paper describes an approach for verifying the susceptibility of CMOS latches to heavy-ion induced state changes. The approach utilizes alpha particles to induce the upsets in test circuits. These test circuits are standard cells that have offset voltages which sensitize the circuits to upsets. These results are then used to calculate the upsetability at operating voltages. In this study results are presented for the alpha particle upset of a six-transistor static random access memory (SRAM) cell. Then a methodology is described for the analysis of a standard-cell inverter latch.

Buehler, M.↗