NASA NTRS · 19860019793
MOS integrated circuit fault modeling
Abstract
Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.
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Sievers, M.. 1985-06-01. MOS integrated circuit fault modeling. https://ntrs.nasa.gov/citations/19860019793
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