Engineering topics
Sievers, M.
Publications and source records attributed to Sievers, M..
MOS integrated circuit fault modeling
Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.
An algorithm for generating an m-ary summation tree
An algorithm is presented for generating an m-ary summation tree. The algorithm is completely general and may be applied to any length input string. For an N length sequence summed in groups of m sub l at each level l a maximum of 3L - 2 storage is required. A special case of the general m-ary tree where all m sub l are equal is used to smooth data in a radio frequency interference experiment. The maximum storage required when m l sub l = m for all l reduces to the closed form 3 log m N - 2.