Engineering topics
Publications and source records attributed to Timoc, C. C..
Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.
Report describes technique using fault simulator implemented entirely in hardware to generate and optimize test vectors for microprocessor. Hardware fault simulator approach reduces test time, while maintaining high reliability in detecting faults.
Breadboarded circuit is faster and more thorough than software simulator. Elementary fault simulator for AND gate uses three gates and shaft register to simulate stuck-at-one or stuck-at-zero conditions at inputs and output. Experimental results showed hardware fault simulator for microprocessor gave faster results than software simulator, by two orders of magnitude, with one test being applied every 4 microseconds.
The stuck fault detection efficiency of the test vectors developed for the MIL-M-38510/470 NASA was measured using a hardware stuck fault simulator for the 1802 microprocessor. Thirty-nine stuck faults were not detected out of a total of 874 injected into the combinatorial and sequential parts of the microprocessor. Since undetected faults can create catastrophic errors in equipment designed for high reliability applications, it is recommended that the MIL-M-38510/470 NASA be enhanced with additional test vectors so as to achieve 100% stuck fault detection efficiency.
This paper describes a method for generating and optimizing test vectors for a microprocessor, with the aid of a fault simulator implemented entirely by hardware. The development and optimization of test vectors has been done on a tester, with the fault simulator plugged directly into the test head. The fault simulator is capable of automatically injecting over a thousand single or multiple stuck faults in the sequential and combinatorial parts of the microprocessor. The test vectors developed by a programmer working interactively with the tester were applied through the tester to the fault simulator, and the percent of faults detected was measured. The vectors were developed and optimized for the 1802 microprocessor, with the objective of detecting 100% of the single stuck faults with a minimum set of vectors. Experimental results show that 99.7% of the single stuck faults are being detected with approximately 14,000 vectors.