Engineering topics
Publications and source records attributed to Zamani, N..
The widths of refractory-gate metal lines were measured as a function of design width W(sub i) and design spacing S(sub j) using an electrical test structure, the Cross-Quad-Bridge.
A test chip set being developed to aid in the qualification of spaceborne Application Specific Integrated Circuits (ASICs) is described. The chip set consists of a process monitor for process parameter verification, a fault chip for yield analysis, a reliability chip for ASIC failure rate analysis, and total ionizing dose and single event upset chips for radiation effect analysis. The test structures contained in these chips are discussed along with representative test results.
Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.
The nondestructive measurement of the chemical and physical characteristics of the interface between bulk SiO2 and thick aluminum films is reported. Both X-ray phototelectron spectroscopy (XPS) and electrical measurements of unannealed, resistively evaporated Al films on thermal SiO2 indicate an atomically abrupt interface. Post metallization annealing at 450 C induces reduction of the SiO2 by the aluminum, at a rate consistent with the bulk reaction rate. The XPS measurement is performed from the SiO2 side after the removal of the Si substrate with XeF2 gas and thinning of the SiO2 layer with HF:ETOH. This represents a powerful new approach to the study of metal-insulator and related interfaces.
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Thin-oxide (40-50 A) metal oxide semiconductor (MOS) structures are shown to exhibit, before large levels of electron tunnel injection, the near-ideal behavior predicted for a uniform trapezoidal barrier with thick-oxide properties. The oscillatory field dependence caused by electron-wave interference at the Si/SiO2 interface suggests an abrupt, one-monolayer barrier transition (approximately 2.5 A) consistent with earlier work. After tunnel injection of 10 to the 17th - 5 x 10 to the 18th electrons/sq cm, the barrier undergoes appreciable degradation, leading to enhanced tunneling conductance. Reproducible behavior is observed among different samples. This effect is found to be consistent with the generation of positive states in the region of the oxide near the Si/SiO2 interface (less than 20 A), where the tunneling electrons emerge into the oxide conduction band.
Electron injection technique serves as powerful probe of trapped hole distribution after irradiation because it was determined that electrons only annihilate trapped holes. Other effects, such as other electron traps and interface state generation, are negligible in injection range used. Trap cross sections and densities indicate at least three trap species; interfacial species, dominant bulk species determined to tail off from silicon interface, and lower density and cross section species that may be distributed throughout bulk of oxide.
Convenient method of determining inherent lateral charge non-uniformities along silicon dioxide/silicon interface of metal-oxide-semiconductor (MOS) employs rapid measurement of capacitance of interface as function of voltage at liquid nitrogen temperature. Charge distribution is extracted by fast-Fourier-transform analysis of capacitance voltage (C-V) measurement.
The trapping parameters for holes, and for electrons in the presence of trapped holes, have been measured from a set of wafers with different oxide thickness processed under controlled conditions. The trap cross-sections and densities indicate at least three trap species, including an interfacial species, a dominant bulk species which is determined to tail off from the silicon interface, and a third, lower density bulk species that is distributed throughout the oxide.